diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index d3863c835b0..3b3504b398c 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 |
