diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/compare_float.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/compare_float.ll | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll index f5e8d9d9d6c..e93221b9361 100644 --- a/llvm/test/CodeGen/Mips/msa/compare_float.ll +++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll @@ -525,7 +525,8 @@ define void @bsel_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, %4 = fcmp ogt <4 x float> %1, %2 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] %5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %3 - ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + ; Note that IfSet and IfClr are swapped since the condition is inverted + ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]] store <4 x float> %5, <4 x float>* %d ; CHECK-DAG: st.w [[R4]], 0($4) @@ -546,7 +547,8 @@ define void @bsel_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, %4 = fcmp ogt <2 x double> %1, %2 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] %5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %3 - ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] + ; Note that IfSet and IfClr are swapped since the condition is inverted + ; CHECK-DAG: bsel.v [[R4]], [[R3]], [[R1]] store <2 x double> %5, <2 x double>* %d ; CHECK-DAG: st.d [[R4]], 0($4) @@ -565,7 +567,8 @@ define void @bseli_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, %3 = fcmp ogt <4 x float> %1, %2 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] %4 = select <4 x i1> %3, <4 x float> %1, <4 x float> zeroinitializer - ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] + ; Note that IfSet and IfClr are swapped since the condition is inverted + ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]] store <4 x float> %4, <4 x float>* %d ; CHECK-DAG: st.w [[R4]], 0($4) @@ -584,7 +587,8 @@ define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, %3 = fcmp ogt <2 x double> %1, %2 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] %4 = select <2 x i1> %3, <2 x double> %1, <2 x double> zeroinitializer - ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] + ; Note that IfSet and IfClr are swapped since the condition is inverted + ; CHECK-DAG: bsel.v [[R4]], [[R3:\$w[0-9]+]], [[R1]] store <2 x double> %4, <2 x double>* %d ; CHECK-DAG: st.d [[R4]], 0($4) |
