diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/3r-a.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/3r-a.ll | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index ed41e4759c1..76e760089df 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,7 +1,12 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s + +; It should fail to compile without fp64. +; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: FileCheck -check-prefix=FP32ERROR %s +; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). @llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_add_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 |
