diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll index 3b078d6f70d..ae0504980cc 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; ; Register constraint "r" shouldn't take long long unless ; The target is 64 bit. @@ -7,13 +8,25 @@ define i32 @main() nounwind { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: daddiu $1, $zero, 7 +; CHECK-NEXT: #APP +; CHECK-NEXT: .set push +; CHECK-NEXT: .set at +; CHECK-NEXT: .set macro +; CHECK-NEXT: .set reorder +; CHECK-EMPTY: +; CHECK-NEXT: addiu $1, $1, 3 +; CHECK-EMPTY: +; CHECK-NEXT: .set pop +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: jr $ra +; CHECK-NEXT: addiu $2, $zero, 0 entry: ; r with long long -;CHECK: #APP -;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 -;CHECK: #NO_APP tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind ret i32 0 } |
