diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/Fast-ISel')
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll | 32 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll | 4 |
2 files changed, 31 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll index 290e4ecb740..5594de8177d 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -1,3 +1,4 @@ +; Targets where we should not enable FastISel. ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ @@ -7,8 +8,16 @@ ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s @@ -21,9 +30,26 @@ ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; CHECK: FastISel missed terminator: ret i32 0 +; Valid targets for FastISel. +; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -check-prefix=FISEL +; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -check-prefix=FISEL + +; The CHECK prefix is being used by those targets that do not support FastISel. +; By checking that we don't emit the "FastISel missed terminator..." message, +; we ensure that we do not generate code through FastISel. + +; CHECK-NOT: FastISel missed terminator: ret i64 0 + +; The above CHECK will only be valid as long as we *do* emit the missed +; terminator message for targets that support FastISel. If we add support +; for i64 return values in the future, then the following FISEL check-prefix +; will fail and we will have to come up with a new test. + +; FISEL: FastISel missed terminator: ret i64 0 -define i32 @foo() { +define i64 @foo() { entry: - ret i32 0 + ret i64 0 } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll index ee77d43d2b0..eb592189e60 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll @@ -1,5 +1,5 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -fast-isel -mattr=+fp64 < %s \ -; RUN: -fast-isel-abort=3 +; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ +; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently ; supports AFGR64 only, which uses paired 32 bit registers. |
