diff options
Diffstat (limited to 'llvm/test/CodeGen/MIR')
5 files changed, 8 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir index 0ad0e9d568b..7e7b318009a 100644 --- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -33,7 +33,6 @@ name: test_tlsdesc_callseq_length alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%w0' } diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir index 90f2f3c0999..cb552e5cab3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -13,9 +13,8 @@ # CHECK-LABEL: name: copyprop1 # CHECK: bb.0: # CHECK-NOT: %w20 = COPY -name: copyprop1 -allVRegsAllocated: true -body: | +name: copyprop1 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -28,9 +27,8 @@ body: | # CHECK-LABEL: name: copyprop2 # CHECK: bb.0: # CHECK: %w20 = COPY -name: copyprop2 -allVRegsAllocated: true -body: | +name: copyprop2 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -43,9 +41,8 @@ body: | # CHECK-LABEL: name: copyprop3 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop3 -allVRegsAllocated: true -body: | +name: copyprop3 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -58,9 +55,8 @@ body: | # CHECK-LABEL: name: copyprop4 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop4 -allVRegsAllocated: true -body: | +name: copyprop4 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w0 diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 7a0d2989d56..74ea7c63d4b 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -90,7 +90,6 @@ name: f alignment: 1 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%r0' } diff --git a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir index a83c53e57cd..09bc49c508a 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -10,7 +10,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir index e9f2966688c..5056a05ed1f 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -175,7 +175,6 @@ name: test0a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -220,7 +219,6 @@ body: | name: test0b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -263,7 +261,6 @@ body: | name: test1a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -310,7 +307,6 @@ body: | name: test1b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -357,7 +353,6 @@ body: | name: test2a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -404,7 +399,6 @@ body: | name: test2b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -451,7 +445,6 @@ body: | name: test3 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -498,7 +491,6 @@ body: | name: test4 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -609,7 +601,6 @@ body: | name: testBB alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } |
