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Diffstat (limited to 'llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll b/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll new file mode 100644 index 00000000000..2eb71a17314 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=hexagon -disable-hexagon-shuffle=1 -O2 < %s | FileCheck %s +; Generate vshuff with 3rd param as an Rt8. +; v1:0=vshuff(v0,v1,r7) +; CHECK: vshuff(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]}}) + +target triple = "hexagon" + +@g0 = common global [15 x <16 x i32>] zeroinitializer, align 64 +@g1 = common global <32 x i32> zeroinitializer, align 128 + +; Function Attrs: nounwind +define i32 @f0() #0 { +b0: + %v0 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @g0, i32 0, i32 0), align 64, !tbaa !0 + %v1 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @g0, i32 0, i32 1), align 64, !tbaa !0 + %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v0, <16 x i32> %v1, i32 -2147483648) + store <32 x i32> %v2, <32 x i32>* @g1, align 128, !tbaa !0 + %v3 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32, <32 x i32>*)*)(i32 1024, <32 x i32>* @g1) #0 + ret i32 0 +} + +; Function Attrs: nounwind readnone +declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1 + +declare i32 @f1(...) #0 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone } + +!0 = !{!1, !1, i64 0} +!1 = !{!"omnipotent char", !2, i64 0} +!2 = !{!"Simple C/C++ TBAA"} |
