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-rw-r--r--llvm/test/CodeGen/Hexagon/store_abs.ll27
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/store_abs.ll b/llvm/test/CodeGen/Hexagon/store_abs.ll
new file mode 100644
index 00000000000..5860b4de997
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/store_abs.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -O3 < %s
+; REQUIRES: asserts
+
+; Test that the compiler doesn't assert when attempting to
+; generate a store absolute set insturction where the base
+; register and destination register are same.
+
+target triple = "hexagon-unknown--elf"
+
+%s.0 = type { %s.1, %s.2 }
+%s.1 = type { %s.1*, %s.1* }
+%s.2 = type { %s.3 }
+%s.3 = type { %s.4 }
+%s.4 = type { %s.5, i32, i32, i8* }
+%s.5 = type { i32 }
+
+@g0 = external global %s.0, align 4
+
+; Function Attrs: nounwind
+define void @f0() #0 section ".init.text" {
+b0:
+ store %s.1* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0), %s.1** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0, i32 0), align 4
+ store %s.1* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0), %s.1** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0, i32 1), align 4
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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