diff options
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/ldrd-memoper.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/single-issue-r52.mir | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index ed5255bfbeb..208cf8db99c 100644 --- a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -5,11 +5,11 @@ ; latency regardless of whether they are barriers or not. ; CHECK: ** List Scheduling -; CHECK: SU(2){{.*}}STR{{.*}}Volatile +; CHECK: SU(2){{.*}}STR{{.*}}(volatile ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord -; CHECK: SU(3){{.*}}LDR{{.*}}Volatile +; CHECK: SU(3){{.*}}LDR{{.*}}(volatile ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(2): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord diff --git a/llvm/test/CodeGen/ARM/ldrd-memoper.ll b/llvm/test/CodeGen/ARM/ldrd-memoper.ll index 744fbd5efb8..78121adcfeb 100644 --- a/llvm/test/CodeGen/ARM/ldrd-memoper.ll +++ b/llvm/test/CodeGen/ARM/ldrd-memoper.ll @@ -5,7 +5,7 @@ @b = external global i64* -; CHECK: Formed {{.*}} t2LDRD{{.*}} mem:LD4[%0] LD4[%0+4] +; CHECK: Formed {{.*}} t2LDRD{{.*}} (load 4 from %ir.0), (load 4 from %ir.0 + 4) define i64 @t(i64 %a) nounwind readonly { entry: %0 = load i64*, i64** @b, align 4 diff --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir index ea8cecc5a11..78e2ab035b9 100644 --- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -42,7 +42,7 @@ # CHECK_SWIFT: Latency : 2 # CHECK_R52: Latency : 2 # -# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg; mem:LD4[@g1](dereferenceable) +# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg :: (dereferenceable load 4 from @g1) # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 3 # CHECK_R52: Latency : 4 @@ -57,7 +57,7 @@ # CHECK_SWIFT: Latency : 14 # CHECK_R52: Latency : 8 -# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg; mem:ST4[@g1] +# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg :: (store 4 into @g1) # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 0 # CHECK_R52: Latency : 4 diff --git a/llvm/test/CodeGen/ARM/single-issue-r52.mir b/llvm/test/CodeGen/ARM/single-issue-r52.mir index ba43f02101c..22be6a0eade 100644 --- a/llvm/test/CodeGen/ARM/single-issue-r52.mir +++ b/llvm/test/CodeGen/ARM/single-issue-r52.mir @@ -20,7 +20,7 @@ # CHECK: ********** MI Scheduling ********** # CHECK: ScheduleDAGMILive::schedule starting -# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg; mem:LD32[%A](align=8) +# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg :: (load 32 from %ir.A, align 8) # CHECK: Latency : 8 # CHECK: Single Issue : true; # CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg |
