diff options
Diffstat (limited to 'llvm/test/CodeGen/ARM')
36 files changed, 105 insertions, 105 deletions
diff --git a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index 991051caea7..a35ded5b545 100644 --- a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -9,7 +9,7 @@ @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] ; CHECK-LABEL: dct_luma_sp: -define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) "no-frame-pointer-elim"="true" { +define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) "frame-pointer"="all" { entry: ; Make sure to use base-updating stores for saving callee-saved registers. ; CHECK: push diff --git a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index 79315ab59d4..4b89ea32536 100644 --- a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s ; rdar://8690640 -define i32* @t(i32* %x) nounwind "no-frame-pointer-elim"="true" { +define i32* @t(i32* %x) nounwind "frame-pointer"="all" { entry: ; CHECK-LABEL: t: ; CHECK: push diff --git a/llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll index 340e3f8a80e..e0802a64a87 100644 --- a/llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll +++ b/llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s ; rdar://8728956 -define hidden void @foo() nounwind ssp "no-frame-pointer-elim"="true" { +define hidden void @foo() nounwind ssp "frame-pointer"="all" { entry: ; CHECK-LABEL: foo: ; CHECK: mov r7, sp diff --git a/llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll index f4d1b4de7c5..a568c04f1a8 100644 --- a/llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll +++ b/llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -14,7 +14,7 @@ declare i1 @getbool() declare void @foo(i32) declare i32 @bar(i32) -define i32 @test(i32 %in1, i32 %in2) nounwind "no-frame-pointer-elim"="true" { +define i32 @test(i32 %in1, i32 %in2) nounwind "frame-pointer"="all" { entry: %call = tail call zeroext i1 @getbool() nounwind br i1 %call, label %sw.bb18, label %sw.bb2 diff --git a/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll b/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll index feae48646cd..b0c81c09934 100644 --- a/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll +++ b/llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll @@ -45,6 +45,6 @@ declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() -attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/ARM/Windows/wineh-basic.ll b/llvm/test/CodeGen/ARM/Windows/wineh-basic.ll index 848ffbf506f..c4e809f6dd8 100644 --- a/llvm/test/CodeGen/ARM/Windows/wineh-basic.ll +++ b/llvm/test/CodeGen/ARM/Windows/wineh-basic.ll @@ -36,8 +36,8 @@ declare arm_aapcs_vfpcc i32 @__CxxFrameHandler3(...) declare arm_aapcs_vfpcc void @__std_terminate() local_unnamed_addr -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+strict-align,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+strict-align,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+strict-align,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+strict-align,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { noreturn nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll index 99936cd7eef..e6fc02970e4 100644 --- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll +++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -60,7 +60,7 @@ ; pop {r7, pc} ; ; bx lr -define i32 @foo(i32 %a, i32 %b) "no-frame-pointer-elim"="true" { +define i32 @foo(i32 %a, i32 %b) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: foo: ; ARM-ENABLE: @ %bb.0: ; ARM-ENABLE-NEXT: cmp r0, r1 @@ -188,7 +188,7 @@ declare i32 @doSomething(i32, i32*) ; pop {r4, r7, pc} ; ; bx lr -define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" { +define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: freqSaveAndRestoreOutsideLoop: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -347,7 +347,7 @@ declare i32 @something(...) ; @ %for.exit ; nop ; pop {r4 -define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) "no-frame-pointer-elim"="true" { +define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) "frame-pointer"="all" { ; ARM-LABEL: freqSaveAndRestoreOutsideLoop2: ; ARM: @ %bb.0: @ %entry ; ARM-NEXT: push {r4, r7, lr} @@ -553,7 +553,7 @@ for.end: ; preds = %for.body ; pop {r4, r7, pc} ; ; bx lr -define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" { +define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: loopInfoSaveOutsideLoop: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -749,7 +749,7 @@ declare void @somethingElse(...) ; pop {r4, r7, pc} ; ; bx lr -define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" nounwind { +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) "frame-pointer"="all" nounwind { ; ARM-ENABLE-LABEL: loopInfoRestoreOutsideLoop: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -960,7 +960,7 @@ entry: ; pop {r4, r7, pc} ; ; bx lr -define i32 @inlineAsm(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" { +define i32 @inlineAsm(i32 %cond, i32 %N) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: inlineAsm: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -1138,7 +1138,7 @@ if.end: ; preds = %for.body, %if.else ; mov sp, r7 ; add sp, #12 ; pop {r7, pc} -define i32 @callVariadicFunc(i32 %cond, i32 %N) "no-frame-pointer-elim"="true" { +define i32 @callVariadicFunc(i32 %cond, i32 %N) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: callVariadicFunc: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -1270,7 +1270,7 @@ declare i32 @someVariadicFunc(i32, ...) ; ; bl{{x?}} _abort ; pop -define i32 @noreturn(i8 signext %bad_thing) "no-frame-pointer-elim"="true" { +define i32 @noreturn(i8 signext %bad_thing) "frame-pointer"="all" { ; ARM-ENABLE-LABEL: noreturn: ; ARM-ENABLE: @ %bb.0: @ %entry ; ARM-ENABLE-NEXT: cmp r0, #0 @@ -1354,7 +1354,7 @@ attributes #0 = { noreturn nounwind } ; The only condition for this test is the compilation finishes correctly. ; infiniteloop ; pop -define void @infiniteloop() "no-frame-pointer-elim"="true" { +define void @infiniteloop() "frame-pointer"="all" { ; ARM-LABEL: infiniteloop: ; ARM: @ %bb.0: @ %entry ; ARM-NEXT: push {r4, r5, r7, lr} @@ -1509,7 +1509,7 @@ if.end: ; Another infinite loop test this time with a body bigger than just one block. ; infiniteloop2 ; pop -define void @infiniteloop2() "no-frame-pointer-elim"="true" { +define void @infiniteloop2() "frame-pointer"="all" { entry: br i1 undef, label %if.then, label %if.end @@ -1539,7 +1539,7 @@ if.end: ; Another infinite loop test this time with two nested infinite loop. ; infiniteloop3 ; bx lr -define void @infiniteloop3() "no-frame-pointer-elim"="true" { +define void @infiniteloop3() "frame-pointer"="all" { ; ARM-LABEL: infiniteloop3: ; ARM: @ %bb.0: @ %entry ; ARM-NEXT: mov r0, #0 @@ -1759,7 +1759,7 @@ declare double @llvm.pow.f64(double, double) ; info (like labels named 'line_table) not because it's found a bl instruction. ; ; bl -define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %tmp) "no-frame-pointer-elim"="true" { +define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %tmp) "frame-pointer"="all" { ; ARM-LABEL: debug_info: ; ARM: @ %bb.0: @ %bb ; ARM-NEXT: push {r4, r7, lr} diff --git a/llvm/test/CodeGen/ARM/byval_load_align.ll b/llvm/test/CodeGen/ARM/byval_load_align.ll index d00d926c7a0..141ead6c0ad 100644 --- a/llvm/test/CodeGen/ARM/byval_load_align.ll +++ b/llvm/test/CodeGen/ARM/byval_load_align.ll @@ -22,6 +22,6 @@ entry: declare void @Logger(i8 signext, %struct.ModuleID* byval) #1 -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/ARM/call-tc.ll b/llvm/test/CodeGen/ARM/call-tc.ll index c5cfb9def33..4256cc879e7 100644 --- a/llvm/test/CodeGen/ARM/call-tc.ll +++ b/llvm/test/CodeGen/ARM/call-tc.ll @@ -10,14 +10,14 @@ declare void @g(i32, i32, i32, i32) -define void @t1() "no-frame-pointer-elim"="true" { +define void @t1() "frame-pointer"="all" { ; CHECKELF-LABEL: t1: ; CHECKELF: bl g call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } -define void @t2() "no-frame-pointer-elim"="true" { +define void @t2() "frame-pointer"="all" { ; CHECKV6-LABEL: t2: ; CHECKV6: bx r0 ; CHECKT2D-LABEL: t2: @@ -29,7 +29,7 @@ define void @t2() "no-frame-pointer-elim"="true" { ret void } -define void @t3() "no-frame-pointer-elim"="true" { +define void @t3() "frame-pointer"="all" { ; CHECKV6-LABEL: t3: ; CHECKV6: b _t2 ; CHECKELF-LABEL: t3: @@ -42,7 +42,7 @@ define void @t3() "no-frame-pointer-elim"="true" { } ; Sibcall optimization of expanded libcalls. rdar://8707777 -define double @t4(double %a) nounwind readonly ssp "no-frame-pointer-elim"="true" { +define double @t4(double %a) nounwind readonly ssp "frame-pointer"="all" { entry: ; CHECKV6-LABEL: t4: ; CHECKV6: b _sin @@ -52,7 +52,7 @@ entry: ret double %0 } -define float @t5(float %a) nounwind readonly ssp "no-frame-pointer-elim"="true" { +define float @t5(float %a) nounwind readonly ssp "frame-pointer"="all" { entry: ; CHECKV6-LABEL: t5: ; CHECKV6: b _sinf @@ -66,7 +66,7 @@ declare float @sinf(float) nounwind readonly declare double @sin(double) nounwind readonly -define i32 @t6(i32 %a, i32 %b) nounwind readnone "no-frame-pointer-elim"="true" { +define i32 @t6(i32 %a, i32 %b) nounwind readnone "frame-pointer"="all" { entry: ; CHECKV6-LABEL: t6: ; CHECKV6: b ___divsi3 @@ -80,7 +80,7 @@ entry: ; rdar://8309338 declare void @foo() nounwind -define void @t7() nounwind "no-frame-pointer-elim"="true" { +define void @t7() nounwind "frame-pointer"="all" { entry: ; CHECKT2D-LABEL: t7: ; CHECKT2D: it ne @@ -101,7 +101,7 @@ bb: ; Make sure codegenprep is duplicating ret instructions to enable tail calls. ; rdar://11140249 -define i32 @t8(i32 %x) nounwind ssp "no-frame-pointer-elim"="true" { +define i32 @t8(i32 %x) nounwind ssp "frame-pointer"="all" { entry: ; CHECKT2D-LABEL: t8: ; CHECKT2D-NOT: push @@ -148,7 +148,7 @@ declare i32 @c(i32) @x = external global i32, align 4 -define i32 @t9() nounwind "no-frame-pointer-elim"="true" { +define i32 @t9() nounwind "frame-pointer"="all" { ; CHECKT2D-LABEL: t9: ; CHECKT2D: bl __ZN9MutexLockC1Ev ; CHECKT2D: bl __ZN9MutexLockD1Ev @@ -168,7 +168,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou ; rdar://13827621 ; Correctly preserve the input chain for the tailcall node in the bitcast case, ; otherwise the call to floorf is lost. -define float @libcall_tc_test2(float* nocapture %a, float %b) "no-frame-pointer-elim"="true" { +define float @libcall_tc_test2(float* nocapture %a, float %b) "frame-pointer"="all" { ; CHECKT2D-LABEL: libcall_tc_test2: ; CHECKT2D: bl _floorf ; CHECKT2D: b.w _truncf diff --git a/llvm/test/CodeGen/ARM/cfguard-module-flag.ll b/llvm/test/CodeGen/ARM/cfguard-module-flag.ll index 72f4b026ae0..c8a4256ac52 100644 --- a/llvm/test/CodeGen/ARM/cfguard-module-flag.ll +++ b/llvm/test/CodeGen/ARM/cfguard-module-flag.ll @@ -20,7 +20,7 @@ entry: ; CHECK-NOT: __guard_check_icall_fptr ; CHECK-NOT: __guard_dispatch_icall_fptr } -attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+armv7-a,+dsp,+fp16,+neon,+strict-align,+thumb-mode,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false"} +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+armv7-a,+dsp,+fp16,+neon,+strict-align,+thumb-mode,+vfp3" "unsafe-fp-math"="false" "use-soft-float"="false"} !llvm.module.flags = !{!0} !0 = !{i32 2, !"cfguard", i32 1} diff --git a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll index f917278fad3..74598fba830 100644 --- a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -72,8 +72,8 @@ declare i32 @fn3(...) #1 ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, metadata, metadata) #2 -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll b/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll index 261131032d1..0b707386ff0 100644 --- a/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll +++ b/llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll @@ -19,7 +19,7 @@ entry: ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 1), !dbg !16 } -attributes #0 = { minsize norecurse nounwind optsize readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+hwdiv,+soft-float,-crypto,-neon" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { minsize norecurse nounwind optsize readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+hwdiv,+soft-float,-crypto,-neon" "unsafe-fp-math"="false" "use-soft-float"="true" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} diff --git a/llvm/test/CodeGen/ARM/constantpool-promote.ll b/llvm/test/CodeGen/ARM/constantpool-promote.ll index ac16e600c14..43196561f85 100644 --- a/llvm/test/CodeGen/ARM/constantpool-promote.ll +++ b/llvm/test/CodeGen/ARM/constantpool-promote.ll @@ -203,8 +203,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture r declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i1) local_unnamed_addr declare void @llvm.memmove.p0i16.p0i16.i32(i16*, i16*, i32, i1) local_unnamed_addr -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/ARM/cxx-tlscc.ll b/llvm/test/CodeGen/ARM/cxx-tlscc.ll index 6a66c5f197e..649ed17db05 100644 --- a/llvm/test/CodeGen/ARM/cxx-tlscc.ll +++ b/llvm/test/CodeGen/ARM/cxx-tlscc.ll @@ -33,7 +33,7 @@ declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*) ; THUMB: blx ; THUMB: r4 ; THUMB: pop {{.*}}r4 -define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind "no-frame-pointer-elim"="true" { +define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind "frame-pointer"="all" { %.b.i = load i1, i1* @__tls_guard, align 1 br i1 %.b.i, label %__tls_init.exit, label %init.i @@ -95,7 +95,7 @@ __tls_init.exit: ; CHECK-O0-NOT: vpop ; CHECK-O0-NOT: vldr ; CHECK-O0: pop -define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "no-frame-pointer-elim"="true" { +define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "frame-pointer"="all" { ret i32* @sum1 } @@ -109,7 +109,7 @@ define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind "no-frame-pointer-elim" ; CHECK-O0-NOT: vldr ; CHECK-O0: pop declare cxx_fast_tlscc void @tls_helper() -define cxx_fast_tlscc %class.C* @tls_test2() #1 "no-frame-pointer-elim"="true" { +define cxx_fast_tlscc %class.C* @tls_test2() #1 "frame-pointer"="all" { call cxx_fast_tlscc void @tls_helper() ret %class.C* @tC } @@ -119,7 +119,7 @@ define cxx_fast_tlscc %class.C* @tls_test2() #1 "no-frame-pointer-elim"="true" { declare %class.C* @_ZN1CD1Ev(%class.C* readnone returned %this) ; CHECK-LABEL: tls_test ; CHECK: bl __tlv_atexit -define cxx_fast_tlscc void @__tls_test() "no-frame-pointer-elim"="true" { +define cxx_fast_tlscc void @__tls_test() "frame-pointer"="all" { entry: store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4 %0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1 @@ -127,7 +127,7 @@ entry: } declare void @somefunc() -define cxx_fast_tlscc void @test_ccmismatch_notail() "no-frame-pointer-elim"="true" { +define cxx_fast_tlscc void @test_ccmismatch_notail() "frame-pointer"="all" { ; A tail call is not possible here because somefunc does not preserve enough ; registers. ; CHECK-LABEL: test_ccmismatch_notail: @@ -138,7 +138,7 @@ define cxx_fast_tlscc void @test_ccmismatch_notail() "no-frame-pointer-elim"="tr } declare cxx_fast_tlscc void @some_fast_tls_func() -define void @test_ccmismatch_tail() "no-frame-pointer-elim"="true" { +define void @test_ccmismatch_tail() "frame-pointer"="all" { ; We can perform a tail call here because some_fast_tls_func preserves all ; necessary registers (and more). ; CHECK-LABEL: test_ccmismatch_tail: @@ -148,5 +148,5 @@ define void @test_ccmismatch_tail() "no-frame-pointer-elim"="true" { ret void } -attributes #0 = { nounwind "no-frame-pointer-elim"="true" } +attributes #0 = { nounwind "frame-pointer"="all" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/ARM/debug-info-arg.ll b/llvm/test/CodeGen/ARM/debug-info-arg.ll index 73460987641..cfff5230e1d 100644 --- a/llvm/test/CodeGen/ARM/debug-info-arg.ll +++ b/llvm/test/CodeGen/ARM/debug-info-arg.ll @@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios" %struct.tag_s = type { i32, i32, i32 } -define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp "no-frame-pointer-elim"="true" !dbg !1 { +define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp "frame-pointer"="all" !dbg !1 { tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, metadata !5, metadata !DIExpression()), !dbg !20 tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21 tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22 diff --git a/llvm/test/CodeGen/ARM/disable-fp-elim.ll b/llvm/test/CodeGen/ARM/disable-fp-elim.ll index ddbe36597e1..15c1c9231a4 100644 --- a/llvm/test/CodeGen/ARM/disable-fp-elim.ll +++ b/llvm/test/CodeGen/ARM/disable-fp-elim.ll @@ -22,4 +22,4 @@ entry: declare i32 @foo2(i32) -attributes #0 = { nounwind "no-frame-pointer-elim"="true" } +attributes #0 = { nounwind "frame-pointer"="all" } diff --git a/llvm/test/CodeGen/ARM/dwarf-unwind.ll b/llvm/test/CodeGen/ARM/dwarf-unwind.ll index 58a116bdeb0..d537a9779af 100644 --- a/llvm/test/CodeGen/ARM/dwarf-unwind.ll +++ b/llvm/test/CodeGen/ARM/dwarf-unwind.ll @@ -69,7 +69,7 @@ define void @test_nodpr_noalign(i8 %l, i8 %r) { ret void } -define void @test_frame_pointer_offset() minsize "no-frame-pointer-elim"="true" { +define void @test_frame_pointer_offset() minsize "frame-pointer"="all" { ; CHECK-LABEL: test_frame_pointer_offset: ; CHECK: push {r4, r5, r6, r7, lr} ; CHECK: .cfi_def_cfa_offset 20 diff --git a/llvm/test/CodeGen/ARM/early-cfi-sections.ll b/llvm/test/CodeGen/ARM/early-cfi-sections.ll index 5b497fc3502..72b87025a0c 100644 --- a/llvm/test/CodeGen/ARM/early-cfi-sections.ll +++ b/llvm/test/CodeGen/ARM/early-cfi-sections.ll @@ -13,7 +13,7 @@ entry: ret void, !dbg !10 } -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="arm7tdmi" "target-features"="+soft-float,+strict-align,-crypto,-neon" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="arm7tdmi" "target-features"="+soft-float,+strict-align,-crypto,-neon" "unsafe-fp-math"="false" "use-soft-float"="true" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} diff --git a/llvm/test/CodeGen/ARM/global-merge-1.ll b/llvm/test/CodeGen/ARM/global-merge-1.ll index 67eec4b9cb0..68b346ec9f0 100644 --- a/llvm/test/CodeGen/ARM/global-merge-1.ll +++ b/llvm/test/CodeGen/ARM/global-merge-1.ll @@ -74,9 +74,9 @@ define internal i32* @returnFoo() #2 { ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 0) } -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind readnone ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind readnone ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #3 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/ARM/hello.ll b/llvm/test/CodeGen/ARM/hello.ll index bdeb41decc8..429a6b0efac 100644 --- a/llvm/test/CodeGen/ARM/hello.ll +++ b/llvm/test/CodeGen/ARM/hello.ll @@ -9,7 +9,7 @@ @str = internal constant [12 x i8] c"Hello World\00" -define i32 @main() "no-frame-pointer-elim"="true" { +define i32 @main() "frame-pointer"="all" { %tmp = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0] ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll index bfeae51a87f..79b9900fa9c 100644 --- a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll +++ b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll @@ -35,7 +35,7 @@ declare i8* @bar(i32, i8*, i8*) ; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}: ; CHECK-PROB: successors: %bb.3(0x40000000), %bb.5(0x40000000) -define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "no-frame-pointer-elim"="true" { +define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" { entry: %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) %dst2 = call i8* @bar(i32 2, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) diff --git a/llvm/test/CodeGen/ARM/ifcvt10.ll b/llvm/test/CodeGen/ARM/ifcvt10.ll index a6334127411..9da13557751 100644 --- a/llvm/test/CodeGen/ARM/ifcvt10.ll +++ b/llvm/test/CodeGen/ARM/ifcvt10.ll @@ -4,7 +4,7 @@ ; micro-coded and would have long issue latency even if predicated on ; false predicate. -define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind "no-frame-pointer-elim"="true" { +define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind "frame-pointer"="all" { entry: ; CHECK-LABEL: t: ; CHECK: vpop {d8} diff --git a/llvm/test/CodeGen/ARM/ifcvt5.ll b/llvm/test/CodeGen/ARM/ifcvt5.ll index 3819bc218a9..20df7cef9ba 100644 --- a/llvm/test/CodeGen/ARM/ifcvt5.ll +++ b/llvm/test/CodeGen/ARM/ifcvt5.ll @@ -4,14 +4,14 @@ @x = external global i32* ; <i32**> [#uses=1] -define void @foo(i32 %a) "no-frame-pointer-elim"="true" { +define void @foo(i32 %a) "frame-pointer"="all" { entry: %tmp = load i32*, i32** @x ; <i32*> [#uses=1] store i32 %a, i32* %tmp ret void } -define i32 @t1(i32 %a, i32 %b) "no-frame-pointer-elim"="true" { +define i32 @t1(i32 %a, i32 %b) "frame-pointer"="all" { ; A8-LABEL: t1: ; A8: bxlt lr diff --git a/llvm/test/CodeGen/ARM/insn-sched1.ll b/llvm/test/CodeGen/ARM/insn-sched1.ll index 120252d96d8..ca1cf6469c0 100644 --- a/llvm/test/CodeGen/ARM/insn-sched1.ll +++ b/llvm/test/CodeGen/ARM/insn-sched1.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null ; RUN: llc -mtriple=arm-apple-ios -mattr=+v6 %s -o - | FileCheck %s -define i32 @test(i32 %x) "no-frame-pointer-elim"="true" { +define i32 @test(i32 %x) "frame-pointer"="all" { %tmp = trunc i32 %x to i16 ; <i16> [#uses=1] %tmp2 = call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1] ret i32 %tmp2 diff --git a/llvm/test/CodeGen/ARM/ldrd.ll b/llvm/test/CodeGen/ARM/ldrd.ll index 4cdafa72f62..b4325c78dbf 100644 --- a/llvm/test/CodeGen/ARM/ldrd.ll +++ b/llvm/test/CodeGen/ARM/ldrd.ll @@ -15,7 +15,7 @@ declare i64* @get_ptr() declare void @use_i64(i64 %v) -define void @test_ldrd(i64 %a) nounwind readonly "no-frame-pointer-elim"="true" { +define void @test_ldrd(i64 %a) nounwind readonly "frame-pointer"="all" { ; CHECK-LABEL: test_ldrd: ; NORMAL: bl{{x?}} _get_ptr ; A8: ldrd r0, r1, [r0] @@ -49,7 +49,7 @@ define void @test_ldrd(i64 %a) nounwind readonly "no-frame-pointer-elim"="true" ; GREEDY: %bb ; GREEDY: ldrd ; GREEDY: str -define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind "no-frame-pointer-elim"="true" { +define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind "frame-pointer"="all" { entry: %0 = add nsw i32 %n, -1 ; <i32> [#uses=2] %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] @@ -79,7 +79,7 @@ return: ; preds = %bb, %entry @TestVar = external global %struct.Test ; CHECK-LABEL: Func1: -define void @Func1() nounwind ssp "no-frame-pointer-elim"="true" { +define void @Func1() nounwind ssp "frame-pointer"="all" { entry: ; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} ; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}} @@ -104,7 +104,7 @@ declare void @extfunc(i32, i32, i32, i32) ; A8: ldrd ; CHECK: bl{{x?}} _extfunc ; A8: pop -define void @Func2(i32* %p) "no-frame-pointer-elim"="true" { +define void @Func2(i32* %p) "frame-pointer"="all" { entry: %addr0 = getelementptr i32, i32* %p, i32 0 %addr1 = getelementptr i32, i32* %p, i32 1 @@ -129,7 +129,7 @@ entry: ; GREEDY: ldrd r1, r2, [sp] ; CONSERVATIVE: ldrd r1, r2, [sp] ; CHECK: bl{{x?}} _extfunc -define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { +define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) "frame-pointer"="all" { ; force %v0 and %v1 to be spilled call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{lr}"() ; force the reloaded %v0, %v1 into different registers @@ -143,7 +143,7 @@ declare void @extfunc2(i32*, i32, i32) ; NORMAL: ldrd r1, r2, [r0], #-8 ; CONSERVATIVE-NOT: ldrd ; CHECK: bl{{x?}} _extfunc -define void @ldrd_postupdate_dec(i32* %p0) "no-frame-pointer-elim"="true" { +define void @ldrd_postupdate_dec(i32* %p0) "frame-pointer"="all" { %p0.1 = getelementptr i32, i32* %p0, i32 1 %v0 = load i32, i32* %p0 %v1 = load i32, i32* %p0.1 @@ -156,7 +156,7 @@ define void @ldrd_postupdate_dec(i32* %p0) "no-frame-pointer-elim"="true" { ; NORMAL: ldrd r1, r2, [r0], #8 ; CONSERVATIVE-NOT: ldrd ; CHECK: bl{{x?}} _extfunc -define void @ldrd_postupdate_inc(i32* %p0) "no-frame-pointer-elim"="true" { +define void @ldrd_postupdate_inc(i32* %p0) "frame-pointer"="all" { %p0.1 = getelementptr i32, i32* %p0, i32 1 %v0 = load i32, i32* %p0 %v1 = load i32, i32* %p0.1 @@ -169,7 +169,7 @@ define void @ldrd_postupdate_inc(i32* %p0) "no-frame-pointer-elim"="true" { ; NORMAL: strd r1, r2, [r0], #-8 ; CONSERVATIVE-NOT: strd ; CHECK: bx lr -define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { +define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" { %p0.1 = getelementptr i32, i32* %p0, i32 1 store i32 %v0, i32* %p0 store i32 %v1, i32* %p0.1 @@ -181,7 +181,7 @@ define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "no-frame-pointer-e ; NORMAL: strd r1, r2, [r0], #8 ; CONSERVATIVE-NOT: strd ; CHECK: bx lr -define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { +define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" { %p0.1 = getelementptr i32, i32* %p0, i32 1 store i32 %v0, i32* %p0 store i32 %v1, i32* %p0.1 diff --git a/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll b/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll index d197a3757b2..c318a3b1868 100644 --- a/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll +++ b/llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll @@ -110,5 +110,5 @@ for.end22.i.i: ; preds = %for.body14.i.i declare i32 @__gxx_personality_v0(...) -attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll index c4fe8dc6487..a9a353cad57 100644 --- a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll +++ b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -15,7 +15,7 @@ target triple = "thumbv7-apple-ios" %struct.partition_entry = type { i32, i32, i64, i64 } -define i32 @partition_overlap_check(%struct.partition_entry* nocapture %part, i32 %num_entries) nounwind readonly optsize ssp "no-frame-pointer-elim"="true" { +define i32 @partition_overlap_check(%struct.partition_entry* nocapture %part, i32 %num_entries) nounwind readonly optsize ssp "frame-pointer"="all" { entry: %cmp79 = icmp sgt i32 %num_entries, 0 br i1 %cmp79, label %outer.loop, label %for.end72 diff --git a/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll b/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll index f93a9ae6a07..f8ba5451255 100644 --- a/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll +++ b/llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll @@ -90,7 +90,7 @@ define void @test3(%struct.S* %d, %struct.S* %s) #0 { declare void @g(i32*) ; Set "no-frame-pointer-elim" to increase register pressure -attributes #0 = { "no-frame-pointer-elim"="true" } +attributes #0 = { "frame-pointer"="all" } ; Function Attrs: nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) #1 diff --git a/llvm/test/CodeGen/ARM/memfunc.ll b/llvm/test/CodeGen/ARM/memfunc.ll index 6c0668a53e8..0fe1f630c57 100644 --- a/llvm/test/CodeGen/ARM/memfunc.ll +++ b/llvm/test/CodeGen/ARM/memfunc.ll @@ -8,7 +8,7 @@ ; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK ; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK -define void @f1(i8* %dest, i8* %src) "no-frame-pointer-elim"="true" { +define void @f1(i8* %dest, i8* %src) "frame-pointer"="all" { entry: ; CHECK-LABEL: f1 @@ -98,7 +98,7 @@ entry: } ; Check that alloca arguments to memory intrinsics are automatically aligned if at least 8 bytes in size -define void @f2(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f2(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f2 @@ -144,7 +144,7 @@ entry: } ; Check that alloca arguments are not aligned if less than 8 bytes in size -define void @f3(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f3(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f3 @@ -183,7 +183,7 @@ entry: } ; Check that alloca arguments are not aligned if size+offset is less than 8 bytes -define void @f4(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f4(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f4 @@ -222,7 +222,7 @@ entry: } ; Check that alloca arguments are not aligned if the offset is not a multiple of 4 -define void @f5(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f5(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f5 @@ -261,7 +261,7 @@ entry: } ; Check that alloca arguments are not aligned if the offset is unknown -define void @f6(i8* %dest, i32 %n, i32 %i) "no-frame-pointer-elim"="true" { +define void @f6(i8* %dest, i32 %n, i32 %i) "frame-pointer"="all" { entry: ; CHECK-LABEL: f6 @@ -300,7 +300,7 @@ entry: } ; Check that alloca arguments are not aligned if the GEP is not inbounds -define void @f7(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f7(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f7 @@ -339,7 +339,7 @@ entry: } ; Check that alloca arguments are not aligned when the offset is past the end of the allocation -define void @f8(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f8(i8* %dest, i32 %n) "frame-pointer"="all" { entry: ; CHECK-LABEL: f8 @@ -389,7 +389,7 @@ entry: @arr8 = internal global [128 x i8] undef @arr9 = weak_odr global [128 x i8] undef @arr10 = dso_local global [8 x i8] c"\01\02\03\04\05\06\07\08", align 1 -define void @f9(i8* %dest, i32 %n) "no-frame-pointer-elim"="true" { +define void @f9(i8* %dest, i32 %n) "frame-pointer"="all" { entry: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr1, i32 0, i32 0), i32 %n, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr2, i32 0, i32 0), i32 %n, i1 false) diff --git a/llvm/test/CodeGen/ARM/noreturn.ll b/llvm/test/CodeGen/ARM/noreturn.ll index f242afb9953..97327082de5 100644 --- a/llvm/test/CodeGen/ARM/noreturn.ll +++ b/llvm/test/CodeGen/ARM/noreturn.ll @@ -61,7 +61,7 @@ entry: } -define i32 @test1_nofpelim() "no-frame-pointer-elim"="true" { +define i32 @test1_nofpelim() "frame-pointer"="all" { ; CHECK-LABEL: @test1_nofpelim ; CHECK: push entry: @@ -69,7 +69,7 @@ entry: unreachable } -define i32 @test2_nofpelim(i32 %x, i32 %y) "no-frame-pointer-elim"="true" { +define i32 @test2_nofpelim(i32 %x, i32 %y) "frame-pointer"="all" { ; CHECK-LABEL: @test2_nofpelim ; CHECK: push entry: @@ -90,7 +90,7 @@ if.end: ; preds = %entry } ; Test case for PR17825. -define i32 @test3_nofpelim() "no-frame-pointer-elim"="true" { +define i32 @test3_nofpelim() "frame-pointer"="all" { ; CHECK-LABEL: @test3_nofpelim ; CHECK: push entry: @@ -99,7 +99,7 @@ entry: } ; Test case for uwtable -define i32 @test4_nofpelim() uwtable "no-frame-pointer-elim"="true" { +define i32 @test4_nofpelim() uwtable "frame-pointer"="all" { ; CHECK-LABEL: @test4_nofpelim ; CHECK: push entry: @@ -107,7 +107,7 @@ entry: unreachable } -define i32 @test5_nofpelim() uwtable "no-frame-pointer-elim"="true" { +define i32 @test5_nofpelim() uwtable "frame-pointer"="all" { ; CHECK-LABEL: @test5_nofpelim ; CHECK: push entry: diff --git a/llvm/test/CodeGen/ARM/stack-size-section.ll b/llvm/test/CodeGen/ARM/stack-size-section.ll index 10f156439e3..7f687bba901 100644 --- a/llvm/test/CodeGen/ARM/stack-size-section.ll +++ b/llvm/test/CodeGen/ARM/stack-size-section.ll @@ -29,4 +29,4 @@ define void @dynalloc(i32 %N) #0 { ret void } -attributes #0 = { "no-frame-pointer-elim"="true" } +attributes #0 = { "frame-pointer"="all" } diff --git a/llvm/test/CodeGen/ARM/stack_guard_remat.ll b/llvm/test/CodeGen/ARM/stack_guard_remat.ll index 9b5677608d2..eb6538603e1 100644 --- a/llvm/test/CodeGen/ARM/stack_guard_remat.ll +++ b/llvm/test/CodeGen/ARM/stack_guard_remat.ll @@ -67,4 +67,4 @@ declare void @foo3(i32*) ; Function Attrs: nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/swiftself.ll b/llvm/test/CodeGen/ARM/swiftself.ll index 1e06b34c705..6db0ae8114f 100644 --- a/llvm/test/CodeGen/ARM/swiftself.ll +++ b/llvm/test/CodeGen/ARM/swiftself.ll @@ -7,7 +7,7 @@ ; Parameter with swiftself should be allocated to r10. ; CHECK-LABEL: swiftself_param: ; CHECK: mov r0, r10 -define i8 *@swiftself_param(i8* swiftself %addr0) "no-frame-pointer-elim"="true" { +define i8 *@swiftself_param(i8* swiftself %addr0) "frame-pointer"="all" { ret i8 *%addr0 } @@ -15,7 +15,7 @@ define i8 *@swiftself_param(i8* swiftself %addr0) "no-frame-pointer-elim"="true" ; CHECK-LABEL: call_swiftself: ; CHECK: mov r10, r0 ; CHECK: bl {{_?}}swiftself_param -define i8 *@call_swiftself(i8* %arg) "no-frame-pointer-elim"="true" { +define i8 *@call_swiftself(i8* %arg) "frame-pointer"="all" { %res = call i8 *@swiftself_param(i8* swiftself %arg) ret i8 *%res } @@ -25,7 +25,7 @@ define i8 *@call_swiftself(i8* %arg) "no-frame-pointer-elim"="true" { ; CHECK: push {r10} ; ... ; CHECK: pop {r10} -define i8 *@swiftself_clobber(i8* swiftself %addr0) "no-frame-pointer-elim"="true" { +define i8 *@swiftself_clobber(i8* swiftself %addr0) "frame-pointer"="all" { call void asm sideeffect "", "~{r10}"() ret i8 *%addr0 } @@ -37,7 +37,7 @@ define i8 *@swiftself_clobber(i8* swiftself %addr0) "no-frame-pointer-elim"="tru ; OPT: bl {{_?}}swiftself_param ; OPT-NOT: mov{{.*}}r10 ; OPT-NEXT: bl {{_?}}swiftself_param -define void @swiftself_passthrough(i8* swiftself %addr0) "no-frame-pointer-elim"="true" { +define void @swiftself_passthrough(i8* swiftself %addr0) "frame-pointer"="all" { call i8 *@swiftself_param(i8* swiftself %addr0) call i8 *@swiftself_param(i8* swiftself %addr0) ret void @@ -47,7 +47,7 @@ define void @swiftself_passthrough(i8* swiftself %addr0) "no-frame-pointer-elim" ; CHECK-LABEL: swiftself_tail: ; TAILCALL: b {{_?}}swiftself_param ; TAILCALL-NOT: pop -define i8* @swiftself_tail(i8* swiftself %addr0) "no-frame-pointer-elim"="true" { +define i8* @swiftself_tail(i8* swiftself %addr0) "frame-pointer"="all" { call void asm sideeffect "", "~{r10}"() %res = tail call i8* @swiftself_param(i8* swiftself %addr0) ret i8* %res @@ -59,7 +59,7 @@ define i8* @swiftself_tail(i8* swiftself %addr0) "no-frame-pointer-elim"="true" ; CHECK: mov r10, r0 ; CHECK: bl {{_?}}swiftself_param ; CHECK: pop -define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind "no-frame-pointer-elim"="true" { +define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind "frame-pointer"="all" { %res = tail call i8* @swiftself_param(i8* swiftself %addr1) ret i8* %res } diff --git a/llvm/test/CodeGen/ARM/urem-opt-size.ll b/llvm/test/CodeGen/ARM/urem-opt-size.ll index bcc53604959..a37415d59af 100644 --- a/llvm/test/CodeGen/ARM/urem-opt-size.ll +++ b/llvm/test/CodeGen/ARM/urem-opt-size.ll @@ -113,5 +113,5 @@ entry: declare i32 @GetValue(...) local_unnamed_addr attributes #0 = { minsize nounwind optsize } -attributes #4 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-jump-tables"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a15" "target-features"="+dsp,+hwdiv,+hwdiv-arm,+neon,+vfp4" "use-soft-float"="false" } +attributes #4 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-jump-tables"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a15" "target-features"="+dsp,+hwdiv,+hwdiv-arm,+neon,+vfp4" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/v7k-abi-align.ll b/llvm/test/CodeGen/ARM/v7k-abi-align.ll index a5cdb8f8982..d7a95c0faa1 100644 --- a/llvm/test/CodeGen/ARM/v7k-abi-align.ll +++ b/llvm/test/CodeGen/ARM/v7k-abi-align.ll @@ -2,25 +2,25 @@ %struct = type { i8, i64, i8, double, i8, <2 x float>, i8, <4 x float> } -define i32 @test_i64_align() "no-frame-pointer-elim"="true" { +define i32 @test_i64_align() "frame-pointer"="all" { ; CHECK-LABEL: test_i64_align: ; CHECL: movs r0, #8 ret i32 ptrtoint(i64* getelementptr(%struct, %struct* null, i32 0, i32 1) to i32) } -define i32 @test_f64_align() "no-frame-pointer-elim"="true" { +define i32 @test_f64_align() "frame-pointer"="all" { ; CHECK-LABEL: test_f64_align: ; CHECL: movs r0, #24 ret i32 ptrtoint(double* getelementptr(%struct, %struct* null, i32 0, i32 3) to i32) } -define i32 @test_v2f32_align() "no-frame-pointer-elim"="true" { +define i32 @test_v2f32_align() "frame-pointer"="all" { ; CHECK-LABEL: test_v2f32_align: ; CHECL: movs r0, #40 ret i32 ptrtoint(<2 x float>* getelementptr(%struct, %struct* null, i32 0, i32 5) to i32) } -define i32 @test_v4f32_align() "no-frame-pointer-elim"="true" { +define i32 @test_v4f32_align() "frame-pointer"="all" { ; CHECK-LABEL: test_v4f32_align: ; CHECL: movs r0, #64 ret i32 ptrtoint(<4 x float>* getelementptr(%struct, %struct* null, i32 0, i32 7) to i32) @@ -28,7 +28,7 @@ define i32 @test_v4f32_align() "no-frame-pointer-elim"="true" { ; Key point here is than an extra register has to be saved so that the DPRs end ; up in an aligned location (as prologue/epilogue inserter had calculated). -define void @test_dpr_unwind_align() "no-frame-pointer-elim"="true" { +define void @test_dpr_unwind_align() "frame-pointer"="all" { ; CHECK-LABEL: test_dpr_unwind_align: ; CHECK: push {r5, r6, r7, lr} ; CHECK-NOT: sub sp @@ -51,7 +51,7 @@ define void @test_dpr_unwind_align() "no-frame-pointer-elim"="true" { ; This time, there's no viable way to tack CS-registers onto the list: a real SP ; adjustment needs to be performed to put d8 and d9 where they should be. -define void @test_dpr_unwind_align_manually() "no-frame-pointer-elim"="true" { +define void @test_dpr_unwind_align_manually() "frame-pointer"="all" { ; CHECK-LABEL: test_dpr_unwind_align_manually: ; CHECK: push {r4, r5, r6, r7, lr} ; CHECK-NOT: sub sp @@ -76,7 +76,7 @@ define void @test_dpr_unwind_align_manually() "no-frame-pointer-elim"="true" { } ; If there's only a CS1 area, the sub should be in the right place: -define void @test_dpr_unwind_align_just_cs1() "no-frame-pointer-elim"="true" { +define void @test_dpr_unwind_align_just_cs1() "frame-pointer"="all" { ; CHECK-LABEL: test_dpr_unwind_align_just_cs1: ; CHECK: push {r4, r5, r6, r7, lr} ; CHECK: sub sp, #4 @@ -99,7 +99,7 @@ define void @test_dpr_unwind_align_just_cs1() "no-frame-pointer-elim"="true" { } ; If there are no DPRs, we shouldn't try to align the stack in stages anyway -define void @test_dpr_unwind_align_no_dprs() "no-frame-pointer-elim"="true" { +define void @test_dpr_unwind_align_no_dprs() "frame-pointer"="all" { ; CHECK-LABEL: test_dpr_unwind_align_no_dprs: ; CHECK: push {r4, r5, r6, r7, lr} ; CHECK: sub sp, #12 @@ -117,7 +117,7 @@ define void @test_dpr_unwind_align_no_dprs() "no-frame-pointer-elim"="true" { ; 128-bit vectors should use 128-bit (i.e. correctly aligned) slots on ; the stack. -define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) "no-frame-pointer-elim"="true" { +define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) "frame-pointer"="all" { ; CHECK-LABEL: test_v128_stack_pass: ; CHECK: add r[[ADDR:[0-9]+]], sp, #16 ; CHECK: vld1.64 {d0, d1}, [r[[ADDR]]:128] @@ -129,7 +129,7 @@ declare void @varargs(i32, ...) ; When varargs are enabled, we go down a different route. Still want 128-bit ; alignment though. -define void @test_v128_stack_pass_varargs(<4 x float> %in) "no-frame-pointer-elim"="true" { +define void @test_v128_stack_pass_varargs(<4 x float> %in) "frame-pointer"="all" { ; CHECK-LABEL: test_v128_stack_pass_varargs: ; CHECK: add r[[ADDR:[0-9]+]], sp, #16 ; CHECK: vst1.64 {d0, d1}, [r[[ADDR]]:128] @@ -140,7 +140,7 @@ define void @test_v128_stack_pass_varargs(<4 x float> %in) "no-frame-pointer-eli ; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give ; a single pointer), 64-bit quantities must be pass -define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) "no-frame-pointer-elim"="true" { +define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) "frame-pointer"="all" { ; CHECK-LABEL: test_64bit_gpr_align: ; CHECK: ldr [[RHS:r[0-9]+]], [sp] ; CHECK: adds r0, [[RHS]], r2 diff --git a/llvm/test/CodeGen/ARM/warn-stack.ll b/llvm/test/CodeGen/ARM/warn-stack.ll index f07cb64cddf..6756a4b9e3a 100644 --- a/llvm/test/CodeGen/ARM/warn-stack.ll +++ b/llvm/test/CodeGen/ARM/warn-stack.ll @@ -4,7 +4,7 @@ ; <rdar://13987214> ; CHECK-NOT: nowarn -define void @nowarn() nounwind ssp "no-frame-pointer-elim"="true" { +define void @nowarn() nounwind ssp "frame-pointer"="all" { entry: %buffer = alloca [12 x i8], align 1 %arraydecay = getelementptr inbounds [12 x i8], [12 x i8]* %buffer, i64 0, i64 0 @@ -13,7 +13,7 @@ entry: } ; CHECK: warning: stack size limit exceeded (92) in warn -define void @warn() nounwind ssp "no-frame-pointer-elim"="true" { +define void @warn() nounwind ssp "frame-pointer"="all" { entry: %buffer = alloca [80 x i8], align 1 %arraydecay = getelementptr inbounds [80 x i8], [80 x i8]* %buffer, i64 0, i64 0 |
