2 files changed, 128 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/fp16-insert-extract.ll b/llvm/test/CodeGen/ARM/fp16-insert-extract.ll
new file mode 100644
index 00000000000..617a4dfada1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp16-insert-extract.ll
@@ -0,0 +1,72 @@
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
+
+define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
+; CHECK-LABEL: test_vget_lane_f16_1:
+; CHECK:      vmovx.f16 s0, s0
+; CHECK-NEXT: vcvtb.f32.f16 s0, s0
+entry:
+  %elt = extractelement <4 x half> %a, i32 1
+  %conv = fpext half %elt to float
+  ret float %conv
+}
+
+define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
+; CHECK-LABEL: test_vget_lane_f16_2:
+; CHECK-NOT:  vmovx.f16
+; CHECK:      vcvtb.f32.f16 s0, s1
+entry:
+  %elt = extractelement <4 x half> %a, i32 2
+  %conv = fpext half %elt to float
+  ret float %conv
+}
+
+define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
+; CHECK-LABEL: test_vget_laneq_f16_6:
+; CHECK-NOT:  vmovx.f16
+; CHECK:      vcvtb.f32.f16 s0, s3
+entry:
+  %elt = extractelement <8 x half> %a, i32 6
+  %conv = fpext half %elt to float
+  ret float %conv
+}
+
+define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
+; CHECK-LABEL: test_vget_laneq_f16_7:
+; CHECK:      vmovx.f16 s0, s3
+; CHECK:      vcvtb.f32.f16 s0, s0
+entry:
+  %elt = extractelement <8 x half> %a, i32 7
+  %conv = fpext half %elt to float
+  ret float %conv
+}
+
+define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
+; CHECK-LABEL: test_vset_lane_f16:
+; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
+; CHECK: vmov.16  d{{[0-9]+}}[3], r[[GPR]]
+entry:
+  %b = fptrunc float %fb to half
+  %x = insertelement <4 x half> %a, half %b, i32 3
+  ret <4 x half> %x
+}
+
+define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
+; CHECK-LABEL: test_vset_laneq_f16_1:
+; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
+; CHECK: vmov.16  d{{[0-9]+}}[1], r[[GPR]]
+entry:
+  %b = fptrunc float %fb to half
+  %x = insertelement <8 x half> %a, half %b, i32 1
+  ret <8 x half> %x
+}
+
+define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
+; CHECK-LABEL: test_vset_laneq_f16_7:
+; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
+; CHECK: vmov.16  d{{[0-9]+}}[3], r[[GPR]]
+entry:
+  %b = fptrunc float %fb to half
+  %x = insertelement <8 x half> %a, half %b, i32 7
+  ret <8 x half> %x
+}
diff --git a/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll b/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll
new file mode 100644
index 00000000000..2a7358323af
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll
@@ -0,0 +1,56 @@
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
+
+define <4 x half> @vld1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
+; CHECK-LABEL: vld1d_lane_f16:
+; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
+entry:
+  %a = load half, half* %pa
+  %res = insertelement <4 x half> %v4, half %a, i32 3
+  ret <4 x half> %res
+}
+
+define <8 x half> @vld1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
+; CHECK-LABEL: vld1q_lane_f16_1:
+; CHECK: vld1.16 {d{{[0-9]+}}[1]}, [r0:16]
+entry:
+  %a = load half, half* %pa
+  %res = insertelement <8 x half> %v8, half %a, i32 1
+  ret <8 x half> %res
+}
+
+define <8 x half> @vld1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
+; CHECK-LABEL: vld1q_lane_f16_7:
+; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]
+entry:
+  %a = load half, half* %pa
+  %res = insertelement <8 x half> %v8, half %a, i32 7
+  ret <8 x half> %res
+}
+
+define void @vst1d_lane_f16(half* %pa, <4 x half> %v4) nounwind {
+; CHECK-LABEL: vst1d_lane_f16:
+; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
+entry:
+  %a = extractelement <4 x half> %v4, i32 3
+  store half %a, half* %pa
+  ret void
+}
+
+define void @vst1q_lane_f16_7(half* %pa, <8 x half> %v8) nounwind {
+; CHECK-LABEL: vst1q_lane_f16_7:
+; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]
+entry:
+  %a = extractelement <8 x half> %v8, i32 7
+  store half %a, half* %pa
+  ret void
+}
+
+define void @vst1q_lane_f16_1(half* %pa, <8 x half> %v8) nounwind {
+; CHECK-LABEL: vst1q_lane_f16_1:
+; CHECK: vst1.16 {d{{[0-9]+}}[1]}, [r0:16]
+entry:
+  %a = extractelement <8 x half> %v8, i32 1
+  store half %a, half* %pa
+  ret void
+}