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Diffstat (limited to 'llvm/test/CodeGen/ARM/vbits.ll')
-rw-r--r--llvm/test/CodeGen/ARM/vbits.ll118
1 files changed, 59 insertions, 59 deletions
diff --git a/llvm/test/CodeGen/ARM/vbits.ll b/llvm/test/CodeGen/ARM/vbits.ll
index 0a7f7698fa8..2997750ccb1 100644
--- a/llvm/test/CodeGen/ARM/vbits.ll
+++ b/llvm/test/CodeGen/ARM/vbits.ll
@@ -3,7 +3,7 @@
define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: v_andi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vand d16, d17, d16
@@ -17,7 +17,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: v_andi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vand d16, d17, d16
@@ -31,7 +31,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: v_andi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vand d16, d17, d16
@@ -45,7 +45,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-LABEL: v_andi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vand d16, d17, d16
@@ -59,7 +59,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: v_andQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vand q8, q9, q8
@@ -74,7 +74,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: v_andQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vand q8, q9, q8
@@ -89,7 +89,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: v_andQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vand q8, q9, q8
@@ -104,7 +104,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-LABEL: v_andQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vand q8, q9, q8
@@ -119,7 +119,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: v_bici8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vbic d16, d17, d16
@@ -134,7 +134,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: v_bici16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vbic d16, d17, d16
@@ -149,7 +149,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: v_bici32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vbic d16, d17, d16
@@ -164,7 +164,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-LABEL: v_bici64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vbic d16, d17, d16
@@ -179,7 +179,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: v_bicQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vbic q8, q9, q8
@@ -195,7 +195,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: v_bicQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vbic q8, q9, q8
@@ -211,7 +211,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: v_bicQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vbic q8, q9, q8
@@ -227,7 +227,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-LABEL: v_bicQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vbic q8, q9, q8
@@ -243,7 +243,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: v_eori8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: veor d16, d17, d16
@@ -257,7 +257,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: v_eori16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: veor d16, d17, d16
@@ -271,7 +271,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: v_eori32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: veor d16, d17, d16
@@ -285,7 +285,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-LABEL: v_eori64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: veor d16, d17, d16
@@ -299,7 +299,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: v_eorQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: veor q8, q9, q8
@@ -314,7 +314,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: v_eorQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: veor q8, q9, q8
@@ -329,7 +329,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: v_eorQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: veor q8, q9, q8
@@ -344,7 +344,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-LABEL: v_eorQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: veor q8, q9, q8
@@ -359,7 +359,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_mvni8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
@@ -371,7 +371,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
; CHECK-LABEL: v_mvni16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
@@ -383,7 +383,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
; CHECK-LABEL: v_mvni32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
@@ -395,7 +395,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
; CHECK-LABEL: v_mvni64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vmvn d16, d16
; CHECK-NEXT: vmov r0, r1, d16
@@ -407,7 +407,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
; CHECK-LABEL: v_mvnQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmvn q8, q8
; CHECK-NEXT: vmov r0, r1, d16
@@ -420,7 +420,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
; CHECK-LABEL: v_mvnQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmvn q8, q8
; CHECK-NEXT: vmov r0, r1, d16
@@ -433,7 +433,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
; CHECK-LABEL: v_mvnQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmvn q8, q8
; CHECK-NEXT: vmov r0, r1, d16
@@ -446,7 +446,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
; CHECK-LABEL: v_mvnQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vmvn q8, q8
; CHECK-NEXT: vmov r0, r1, d16
@@ -459,7 +459,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: v_orri8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorr d16, d17, d16
@@ -473,7 +473,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: v_orri16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorr d16, d17, d16
@@ -487,7 +487,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: v_orri32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorr d16, d17, d16
@@ -501,7 +501,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-LABEL: v_orri64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorr d16, d17, d16
@@ -515,7 +515,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: v_orrQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorr q8, q9, q8
@@ -530,7 +530,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: v_orrQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorr q8, q9, q8
@@ -545,7 +545,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: v_orrQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorr q8, q9, q8
@@ -560,7 +560,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-LABEL: v_orrQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorr q8, q9, q8
@@ -575,7 +575,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: v_orni8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorn d16, d17, d16
@@ -590,7 +590,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: v_orni16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorn d16, d17, d16
@@ -605,7 +605,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: v_orni32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorn d16, d17, d16
@@ -620,7 +620,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
; CHECK-LABEL: v_orni64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vorn d16, d17, d16
@@ -635,7 +635,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: v_ornQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorn q8, q9, q8
@@ -651,7 +651,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: v_ornQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorn q8, q9, q8
@@ -667,7 +667,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: v_ornQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorn q8, q9, q8
@@ -683,7 +683,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
; CHECK-LABEL: v_ornQi64:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vorn q8, q9, q8
@@ -699,7 +699,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vtsti8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtst.8 d16, d17, d16
@@ -715,7 +715,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vtsti16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtst.16 d16, d17, d16
@@ -731,7 +731,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: vtsti32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vtst.32 d16, d17, d16
@@ -747,7 +747,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vtstQi8:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtst.8 q8, q9, q8
@@ -764,7 +764,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vtstQi16:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtst.16 q8, q9, q8
@@ -781,7 +781,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vtstQi32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vtst.32 q8, q9, q8
@@ -798,7 +798,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_orrimm:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vorr.i32 d16, #0x1000000
; CHECK-NEXT: vmov r0, r1, d16
@@ -810,7 +810,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
; CHECK-LABEL: v_orrimmQ:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vorr.i32 q8, #0x1000000
; CHECK-NEXT: vmov r0, r1, d16
@@ -823,7 +823,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_bicimm:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vbic.i32 d16, #0xff000000
; CHECK-NEXT: vmov r0, r1, d16
@@ -835,7 +835,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
; CHECK-LABEL: v_bicimmQ:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vbic.i32 q8, #0xff000000
; CHECK-NEXT: vmov r0, r1, d16
@@ -848,7 +848,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: hidden_not_v4i32:
-; CHECK: @ BB#0:
+; CHECK: @ %bb.0:
; CHECK-NEXT: vmov d19, r2, r3
; CHECK-NEXT: vmov.i32 q8, #0x6
; CHECK-NEXT: vmov d18, r0, r1
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