diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
28 files changed, 59 insertions, 59 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir index 0a39304d446..72f91e0ffaf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir @@ -15,7 +15,7 @@ ... --- name: test_blockaddress -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir index 17b1e0982e6..dfff28fc63a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir @@ -16,7 +16,7 @@ ... --- name: test_blockaddress -alignment: 4 +alignment: 16 legalized: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 1295a75ed2c..3d1b98714c5 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir @@ -5,7 +5,7 @@ --- name: main -alignment: 0 +alignment: 1 tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index 49b8b1af7d5..e5ff97a7be3 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -5,7 +5,7 @@ # GCN: %10:vgpr_32 = V_MOV_B32_e32 1543, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %10, name: s_fold_and_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -78,7 +78,7 @@ body: | # GCN: FLAT_STORE_DWORD %19, %13, name: v_fold_and_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -168,7 +168,7 @@ body: | # GCN: BUFFER_STORE_DWORD_OFFSET killed %13, name: s_fold_shl_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -257,7 +257,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_shl_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -370,7 +370,7 @@ body: | # GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8, name: s_fold_ashr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -456,7 +456,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_ashr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -578,7 +578,7 @@ body: | # GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8, name: s_fold_lshr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -665,7 +665,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_lshr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -837,7 +837,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %2 name: constant_fold_lshl_or_reg0_immreg_reg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -862,7 +862,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %2 name: constant_fold_lshl_or_reg0_immreg_imm -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -886,7 +886,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %3 name: constant_fold_lshl_or_reg0_immreg_immreg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir index 7d1db87c4b5..4679831c786 100644 --- a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir +++ b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir @@ -150,7 +150,7 @@ ... --- name: _amdgpu_ps_main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir index 66a238dff82..8135de9feba 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir @@ -6,7 +6,7 @@ --- name: main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir index e2f6dc1510d..d31a9c97bdb 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir +++ b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir @@ -24,7 +24,7 @@ ... --- name: flat_load_clustering -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir index 8330a07837d..3ab99551012 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir @@ -114,7 +114,7 @@ # CHECK: %13:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $exec name: add_f32_1.0_one_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -176,7 +176,7 @@ body: | name: add_f32_1.0_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -242,7 +242,7 @@ body: | # CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec name: add_f32_1.0_one_f32_use_one_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -312,7 +312,7 @@ body: | # CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec name: add_f32_1.0_one_f32_use_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -381,7 +381,7 @@ body: | name: add_i32_1_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -446,7 +446,7 @@ body: | # CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $exec name: add_i32_m2_one_f32_use_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -518,7 +518,7 @@ body: | # CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $exec name: add_f16_1.0_multi_f32_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -585,7 +585,7 @@ body: | # CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec name: add_f16_1.0_other_high_bits_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -651,7 +651,7 @@ body: | # CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $exec # CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec name: add_f16_1.0_other_high_bits_use_f16_f32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/hazard.mir b/llvm/test/CodeGen/AMDGPU/hazard.mir index 80fa69b8d6b..bc62bd9ef08 100644 --- a/llvm/test/CodeGen/AMDGPU/hazard.mir +++ b/llvm/test/CodeGen/AMDGPU/hazard.mir @@ -11,7 +11,7 @@ --- name: hazard_implicit_def -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -40,7 +40,7 @@ body: | # GCN: V_INTERP_P1_F32 --- name: hazard_inlineasm -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir index 6159f646b05..9f39dc34150 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir @@ -25,7 +25,7 @@ # CHECK: $vgpr2 = V_MOV_B32 # CHECK: $vgpr3 = V_MOV_B32 name: exp_done_waitcnt -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir index c4cc1c24973..6e67f7df30a 100644 --- a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -514,7 +514,7 @@ body: | ... --- name: mov_fed_hazard_crash_on_dbg_value -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir index b33a6beb6ce..48f0be4ff8f 100644 --- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir +++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir @@ -29,7 +29,7 @@ # CHECK: S_CBRANCH_VCCZ %bb.1, implicit undef $vcc name: invert_br_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir index e698995e435..fbf59da6c2f 100644 --- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir +++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir @@ -16,7 +16,7 @@ --- name: main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir index eed7e049961..f33c2115dcb 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir @@ -52,7 +52,7 @@ # CHECK-NEXT: BUFFER_WBINVL1_VOL name: atomic_max_i32_noret -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir index 65775e35521..bf24ce15acb 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir @@ -65,7 +65,7 @@ # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0, 0 name: multiple_mem_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir index 97f7f74a743..a6088b0677a 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir @@ -45,7 +45,7 @@ # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0 name: multiple_mem_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir index 766b687b758..7a541b20185 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir @@ -25,7 +25,7 @@ ... --- name: scc_def_and_use_no_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -72,7 +72,7 @@ body: | # CHECK: S_ADDC_U32 --- name: scc_def_and_use_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir index 0e31eba262f..becd2e1b9c1 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir @@ -70,7 +70,7 @@ ... --- name: mem_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir index d402ca850d3..3af2f0457fb 100644 --- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir @@ -57,7 +57,7 @@ ... --- name: const_to_sgpr -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -146,7 +146,7 @@ body: | ... --- name: const_to_sgpr_multiple_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -252,7 +252,7 @@ body: | ... --- name: const_to_sgpr_subreg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir index 2e737143ed3..0413075dd86 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir @@ -5,7 +5,7 @@ # GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $exec name: mac_invalid_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -91,7 +91,7 @@ body: | # GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0, # GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0, name: vreg_does_not_dominate -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir index 0b995c680f6..eee471cb073 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir @@ -172,7 +172,7 @@ # CHECK: DBG_VALUE %99, $noreg, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8 name: sched_dbg_value_crash -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir index 3bec72cc538..cd9a909ac7c 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -10,7 +10,7 @@ --- name: mo_pset -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir index d6045a0a2d4..2e96d2129ec 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir +++ b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir @@ -91,7 +91,7 @@ ... --- name: sdwa_imm_operand -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -252,7 +252,7 @@ body: | ... --- name: sdwa_sgpr_operand -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir index d9147609ddd..2aaf7f10b69 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir @@ -11,7 +11,7 @@ # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, 0, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_add_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -95,7 +95,7 @@ body: | # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_sub_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -179,7 +179,7 @@ body: | # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_subrev_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -262,7 +262,7 @@ body: | # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: check_addc_src2_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -347,7 +347,7 @@ body: | # GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: shrink_addc_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -432,7 +432,7 @@ body: | # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: shrink_addc_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir b/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir index ce4a7f9dd6a..f461b1a1159 100644 --- a/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir +++ b/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir @@ -9,7 +9,7 @@ --- name: _amdgpu_cs_main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir index e366a0ebb0e..cda6ecd4650 100644 --- a/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir @@ -22,7 +22,7 @@ # CHECK-NEXT: $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc # CHECK: $exec = COPY killed $sgpr2_sgpr3 name: undefined_physreg_sgpr_spill -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | # CHECK: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5) # CHECK: $exec = COPY killed $sgpr2_sgpr3 name: undefined_physreg_sgpr_spill_reorder -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir index d0a7c57f333..41444b0ef0c 100644 --- a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir +++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir @@ -52,7 +52,7 @@ # CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc name: vccz_corrupt_workaround -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -114,7 +114,7 @@ body: | # CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 name: vccz_corrupt_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/wqm.mir b/llvm/test/CodeGen/AMDGPU/wqm.mir index 6531d625866..a5009cc7924 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.mir +++ b/llvm/test/CodeGen/AMDGPU/wqm.mir @@ -7,7 +7,7 @@ #CHECK: S_CMP_LT_I32 #CHECK: S_CSELECT_B32 name: test_wwm_scc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false |
