diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hoist-cond.ll | 46 |
2 files changed, 48 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll index e12a0b798ee..c8467bb72a6 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -493,9 +493,9 @@ ret: ; GCN: s_setpc_b64 ; GCN: [[LONG_BR_DEST0]] -; GCN: s_cmp_eq_u32 +; GCN: v_cmp_ne_u32_e32 ; GCN-NEXT: ; implicit-def -; GCN-NEXT: s_cbranch_scc0 +; GCN-NEXT: s_cbranch_vccz ; GCN: s_setpc_b64 ; GCN: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/hoist-cond.ll b/llvm/test/CodeGen/AMDGPU/hoist-cond.ll new file mode 100644 index 00000000000..6831f224c91 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hoist-cond.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; Check that invariant compare is hoisted out of the loop. +; At the same time condition shall not be serialized into a VGPR and deserialized later +; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64. + +; CHECK: v_cmp_{{..}}_u32_e64 [[COND:s\[[0-9]+:[0-9]+\]]] +; CHECK: BB0_1: +; CHECK-NOT: v_cmp +; CHECK_NOT: v_cndmask +; CHECK: s_and_saveexec_b64 s[{{[[0-9]+:[0-9]+}}], [[COND]] +; CHECK: BB0_2: + +define amdgpu_kernel void @hoist_cond(float addrspace(1)* nocapture %arg, float addrspace(1)* noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) { +bb: + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 + %tmp5 = icmp ult i32 %tmp, %arg3 + br label %bb1 + +bb1: ; preds = %bb3, %bb + %tmp7 = phi i32 [ %arg4, %bb ], [ %tmp16, %bb3 ] + %tmp8 = phi float [ 0.000000e+00, %bb ], [ %tmp15, %bb3 ] + br i1 %tmp5, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + %tmp10 = zext i32 %tmp7 to i64 + %tmp11 = getelementptr inbounds float, float addrspace(1)* %arg1, i64 %tmp10 + %tmp12 = load float, float addrspace(1)* %tmp11, align 4 + br label %bb3 + +bb3: ; preds = %bb2, %bb1 + %tmp14 = phi float [ %tmp12, %bb2 ], [ 0.000000e+00, %bb1 ] + %tmp15 = fadd float %tmp8, %tmp14 + %tmp16 = add i32 %tmp7, -1 + %tmp17 = icmp eq i32 %tmp16, 0 + br i1 %tmp17, label %bb4, label %bb1 + +bb4: ; preds = %bb3 + store float %tmp15, float addrspace(1)* %arg, align 4 + ret void +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } |
