diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/uniform-cfg.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 71 |
1 files changed, 36 insertions, 35 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll index a462f148847..a5d1cd2281c 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -1,16 +1,17 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=verde -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; GCN-LABEL: {{^}}uniform_if_scc: ; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0 -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -29,17 +30,16 @@ done: } ; GCN-LABEL: {{^}}uniform_if_vcc: -; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and -; also scheduled the write first. ; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) { entry: %cmp0 = fcmp oeq float %cond, 0.0 @@ -59,14 +59,15 @@ done: ; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc: ; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0 -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp eq i32 %cond, 0 @@ -85,17 +86,16 @@ done: } ; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc: -; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and -; also scheduled the write first. ; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) { entry: %cmp0 = fcmp oeq float %cond, 0.0 @@ -276,15 +276,12 @@ bb9: ; preds = %bb8, %bb4 ret void } -; GCN-LABEL: {{^}}uniform_loop: -; GCN: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]: -; FIXME: We need to teach GCNFixSGPRCopies about uniform branches so we -; get s_add_i32 here. -; GCN: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}} -; GCN: v_cmp_ne_u32_e32 vcc, 0, [[I]] -; GCN: s_and_b64 vcc, exec, vcc -; GCN: s_cbranch_vccnz [[LOOP_LABEL]] -; GCN: s_endpgm +; SI-LABEL: {{^}}uniform_loop: +; SI: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]: +; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1 +; SI: s_cmp_lg_u32 [[I]], 0 +; SI: s_cbranch_scc1 [[LOOP_LABEL]] +; SI: s_endpgm define void @uniform_loop(i32 addrspace(1)* %out, i32 %a) { entry: br label %loop @@ -433,7 +430,7 @@ bb9: ; preds = %bb8, %bb4 ; GCN-LABEL: {{^}}uniform_if_scc_i64_eq: ; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; SI: v_cmp_eq_u64_e64 ; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] @@ -441,10 +438,11 @@ bb9: ; preds = %bb8, %bb4 ; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp eq i64 %cond, 0 @@ -464,7 +462,7 @@ done: ; GCN-LABEL: {{^}}uniform_if_scc_i64_ne: ; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 -; GCN-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; SI: v_cmp_ne_u64_e64 ; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] @@ -472,10 +470,11 @@ done: ; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp ne i64 %cond, 0 @@ -494,14 +493,16 @@ done: } ; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt: +; GCN: s_mov_b32 [[S_VAL:s[0-9]+]], 0 ; GCN: v_cmp_gt_i64_e64 ; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] ; Fall-through to the else -; GCN: v_mov_b32_e32 [[STORE_VAL]], 1 +; GCN: s_mov_b32 [[S_VAL]], 1 ; GCN: [[IF_LABEL]]: -; GCN: buffer_store_dword [[STORE_VAL]] +; GCN: v_mov_b32_e32 [[V_VAL]], [[S_VAL]] +; GCN: buffer_store_dword [[V_VAL]] define void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) { entry: %cmp0 = icmp sgt i64 %cond, 0 |
