diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/store-global.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/store-global.ll | 78 |
1 files changed, 52 insertions, 26 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/store-global.ll b/llvm/test/CodeGen/AMDGPU/store-global.ll index f61e524ee2e..35714fe8ee4 100644 --- a/llvm/test/CodeGen/AMDGPU/store-global.ll +++ b/llvm/test/CodeGen/AMDGPU/store-global.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s @@ -10,7 +11,8 @@ ; CM: MEM_RAT MSKOR ; CM-NOT: MEM_RAT MSKOR -; GCN: buffer_store_byte +; SIVI: buffer_store_byte +; GFX9: global_store_byte define amdgpu_kernel void @store_i1(i1 addrspace(1)* %out) { entry: store i1 true, i1 addrspace(1)* %out @@ -40,8 +42,8 @@ entry: ; EG: MOV T[[RW_GPR]].Y, 0.0 ; EG: MOV * T[[RW_GPR]].Z, 0.0 -; GCN: buffer_store_byte - +; SIVI: buffer_store_byte +; GFX9: global_store_byte define amdgpu_kernel void @store_i8(i8 addrspace(1)* %out, i8 %in) { entry: store i8 %in, i8 addrspace(1)* %out @@ -74,7 +76,8 @@ entry: ; EG: MOV T[[RW_GPR]].Y, 0.0 ; EG: MOV * T[[RW_GPR]].Z, 0.0 -; GCN: buffer_store_short +; SIVI: buffer_store_short +; GFX9: global_store_short define amdgpu_kernel void @store_i16(i16 addrspace(1)* %out, i16 %in) { entry: store i16 %in, i16 addrspace(1)* %out @@ -83,8 +86,11 @@ entry: ; FUNC-LABEL: {{^}}store_i24: ; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 -; GCN-DAG: buffer_store_byte -; GCN-DAG: buffer_store_short +; SIVI-DAG: buffer_store_byte +; SIVI-DAG: buffer_store_short + +; GFX9-DAG: global_store_byte +; GFX9-DAG: global_store_short ; EG: MEM_RAT MSKOR ; EG: MEM_RAT MSKOR @@ -97,7 +103,8 @@ entry: ; FUNC-LABEL: {{^}}store_i25: ; GCN: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}} ; GCN: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]] -; GCN: buffer_store_dword [[VAND]] +; SIVI: buffer_store_dword [[VAND]] +; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VAND]] ; EG: MEM_RAT_CACHELESS STORE_RAW ; EG-NOT: MEM_RAT @@ -118,7 +125,8 @@ entry: ; CM: MEM_RAT MSKOR ; CM-NOT: MEM_RAT MSKOR -; GCN: buffer_store_short +; SIVI: buffer_store_short +; GFX9: global_store_short define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i8> @@ -149,7 +157,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dword +; SIVI: buffer_store_dword +; GFX9: global_store_dword define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -168,8 +177,11 @@ entry: ; CM-NOT: MEM_RAT MSKOR ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD -; SI: buffer_store_short -; SI: buffer_store_short +; SIVI: buffer_store_short +; SIVI: buffer_store_short + +; GFX9: global_store_short +; GFX9: global_store_short define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -182,7 +194,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dword +; SIVI: buffer_store_dword +; GFX9: global_store_dword define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i8> @@ -244,7 +257,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} -; GCN: buffer_store_dword +; SIVI: buffer_store_dword +; GFX9: global_store_dword define amdgpu_kernel void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out @@ -256,7 +270,8 @@ define amdgpu_kernel void @store_f32(float addrspace(1)* %out, float %in) { ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}} -; GCN: buffer_store_dwordx2 +; SIVI: buffer_store_dwordx2 +; GFX9: global_store_dwordx2 define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i16> @@ -270,7 +285,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dwordx2 +; SIVI: buffer_store_dwordx2 +; GFX9: global_store_dwordx2 define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { entry: @@ -281,8 +297,11 @@ entry: } ; FUNC-LABEL: {{^}}store_v3i32: -; GCN-DAG: buffer_store_dwordx2 -; GCN-DAG: buffer_store_dword v +; SIVI-DAG: buffer_store_dwordx2 +; SIVI-DAG: buffer_store_dword v + +; GFX9-DAG: global_store_dwordx2 +; GFX9-DAG: global_store_dword v ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XY}}, {{T[0-9]+\.[XYZW]}}, @@ -298,7 +317,8 @@ define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> % ; CM: MEM_RAT_CACHELESS STORE_DWORD ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dwordx4 +; SIVI: buffer_store_dwordx4 +; GFX9: global_store_dwordx4 define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out @@ -312,7 +332,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD -; SI: buffer_store_dwordx4 +; SIVI: buffer_store_dwordx4 +; GFX9: global_store_dwordx4 define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 @@ -327,7 +348,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dwordx4 +; SIVI: buffer_store_dwordx4 +; GFX9: global_store_dwordx4 define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %1 = load <4 x float>, <4 x float> addrspace(1) * %in store <4 x float> %1, <4 x float> addrspace(1)* %out @@ -339,7 +361,8 @@ define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x floa ; CM: MEM_RAT MSKOR -; GCN: buffer_store_byte +; SIVI: buffer_store_byte +; GFX9: global_store_byte define amdgpu_kernel void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -349,7 +372,8 @@ entry: ; FUNC-LABEL: {{^}}store_i64_i16: ; EG: MEM_RAT MSKOR -; GCN: buffer_store_short +; SIVI: buffer_store_short +; GFX9: global_store_short define amdgpu_kernel void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -368,7 +392,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD -; GCN: buffer_store_dwordx2 +; SIVI: buffer_store_dwordx2 +; GFX9: global_store_dwordx2 define amdgpu_kernel void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { entry: %0 = load i32, i32 addrspace(2)* %mem, align 4 @@ -387,7 +412,8 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}, T{{[0-9]+}}.X -; GCN: buffer_store_dwordx4 +; SIVI: buffer_store_dwordx4 +; GFX9: global_store_dwordx4 define amdgpu_kernel void @i128-const-store(i32 addrspace(1)* %out) { entry: store i32 1, i32 addrspace(1)* %out, align 4 |
