diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll b/llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll index 5275a819080..95e88ebfc30 100644 --- a/llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll +++ b/llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 { ; GFX9-LABEL: s_lshr_v2i16: @@ -24,17 +24,17 @@ define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> ; VI-NEXT: s_load_dword s0, s[0:1], 0x30 ; VI-NEXT: s_mov_b32 s4, 0xffff ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_and_b32 s1, s5, s4 -; VI-NEXT: s_and_b32 s4, s0, s4 -; VI-NEXT: s_lshr_b32 s5, s5, 16 -; VI-NEXT: s_lshr_b32 s0, s0, 16 -; VI-NEXT: s_lshr_b32 s0, s5, s0 -; VI-NEXT: v_mov_b32_e32 v0, s4 -; VI-NEXT: v_bfe_u32 v0, s1, v0, 16 -; VI-NEXT: s_lshl_b32 s0, s0, 16 -; VI-NEXT: v_or_b32_e32 v2, s0, v0 ; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: s_lshr_b32 s1, s5, 16 +; VI-NEXT: s_lshr_b32 s6, s0, 16 +; VI-NEXT: s_lshr_b32 s1, s1, s6 +; VI-NEXT: s_and_b32 s5, s5, s4 +; VI-NEXT: s_and_b32 s0, s0, s4 +; VI-NEXT: s_lshr_b32 s0, s5, s0 +; VI-NEXT: s_lshl_b32 s1, s1, 16 +; VI-NEXT: s_or_b32 s0, s0, s1 ; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: s_endpgm ; @@ -49,13 +49,13 @@ define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_lshr_b32 s1, s2, 16 ; CI-NEXT: s_lshr_b32 s8, s0, 16 +; CI-NEXT: s_lshr_b32 s1, s1, s8 +; CI-NEXT: s_and_b32 s2, s2, s3 ; CI-NEXT: s_and_b32 s0, s0, s3 +; CI-NEXT: s_lshr_b32 s0, s2, s0 +; CI-NEXT: s_lshl_b32 s1, s1, 16 +; CI-NEXT: s_or_b32 s0, s0, s1 ; CI-NEXT: v_mov_b32_e32 v0, s0 -; CI-NEXT: s_lshr_b32 s0, s1, s8 -; CI-NEXT: s_and_b32 s2, s2, s3 -; CI-NEXT: v_bfe_u32 v0, s2, v0, 16 -; CI-NEXT: s_lshl_b32 s0, s0, 16 -; CI-NEXT: v_or_b32_e32 v0, s0, v0 ; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; CI-NEXT: s_endpgm %result = lshr <2 x i16> %lhs, %rhs @@ -123,7 +123,7 @@ define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v3, s8, v3 -; CI-NEXT: v_bfe_u32 v2, v2, v3, 16 +; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3 @@ -201,7 +201,7 @@ define amdgpu_kernel void @lshr_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_and_b32_e32 v2, s10, v2 ; CI-NEXT: v_lshrrev_b32_e32 v3, s9, v3 -; CI-NEXT: v_bfe_u32 v2, v2, s8, 16 +; CI-NEXT: v_lshrrev_b32_e32 v2, s8, v2 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 @@ -276,7 +276,7 @@ define amdgpu_kernel void @lshr_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_and_b32_e32 v2, s10, v2 ; CI-NEXT: v_lshr_b32_e32 v3, s9, v3 -; CI-NEXT: v_bfe_u32 v2, s8, v2, 16 +; CI-NEXT: v_lshr_b32_e32 v2, s8, v2 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 @@ -344,7 +344,7 @@ define amdgpu_kernel void @lshr_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 ; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; CI-NEXT: v_lshr_b32_e32 v3, 8, v3 -; CI-NEXT: v_bfe_u32 v2, 8, v2, 16 +; CI-NEXT: v_lshr_b32_e32 v2, 8, v2 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 @@ -490,9 +490,9 @@ define amdgpu_kernel void @v_lshr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> ; CI-NEXT: v_and_b32_e32 v4, s8, v4 ; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v5, s8, v5 -; CI-NEXT: v_bfe_u32 v3, v3, v5, 16 +; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v3 ; CI-NEXT: v_lshrrev_b32_e32 v5, v9, v7 -; CI-NEXT: v_bfe_u32 v2, v2, v4, 16 +; CI-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, v8, v6 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
