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Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/load-hi16.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/load-hi16.ll112
1 files changed, 56 insertions, 56 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
index 8039ec372e4..6ca009bf7f1 100644
--- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
@@ -221,9 +221,9 @@ entry:
; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa
-define void @load_flat_hi_v2i16_reglo_vreg(i16 addrspace(4)* %in, i16 %reg) #0 {
+define void @load_flat_hi_v2i16_reglo_vreg(i16* %in, i16 %reg) #0 {
entry:
- %load = load i16, i16 addrspace(4)* %in
+ %load = load i16, i16* %in
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
@@ -241,9 +241,9 @@ entry:
; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa
-define void @load_flat_hi_v2f16_reglo_vreg(half addrspace(4)* %in, half %reg) #0 {
+define void @load_flat_hi_v2f16_reglo_vreg(half* %in, half %reg) #0 {
entry:
- %load = load half, half addrspace(4)* %in
+ %load = load half, half* %in
%build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef
@@ -261,9 +261,9 @@ entry:
; VI: flat_load_ubyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa
-define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i16 %reg) #0 {
+define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8* %in, i16 %reg) #0 {
entry:
- %load = load i8, i8 addrspace(4)* %in
+ %load = load i8, i8* %in
%ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -282,9 +282,9 @@ entry:
; VI: flat_load_sbyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa
-define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i16 %reg) #0 {
+define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8* %in, i16 %reg) #0 {
entry:
- %load = load i8, i8 addrspace(4)* %in
+ %load = load i8, i8* %in
%ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -301,10 +301,10 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
-define void @load_private_hi_v2i16_reglo_vreg(i16* byval %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
- %gep = getelementptr inbounds i16, i16* %in, i64 2045
- %load = load i16, i16* %gep
+ %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2045
+ %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
@@ -320,10 +320,10 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
-define void @load_private_hi_v2f16_reglo_vreg(half* byval %in, half %reg) #0 {
+define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 {
entry:
- %gep = getelementptr inbounds half, half* %in, i64 2045
- %load = load half, half* %gep
+ %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2045
+ %load = load half, half addrspace(5)* %gep
%build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef
@@ -339,9 +339,9 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
-define void @load_private_hi_v2i16_reglo_vreg_nooff(i16* byval %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
- %load = load volatile i16, i16* inttoptr (i32 4094 to i16*)
+ %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
@@ -357,9 +357,9 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
-define void @load_private_hi_v2f16_reglo_vreg_nooff(half* %in, half %reg) #0 {
+define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 {
entry:
- %load = load volatile half, half* inttoptr (i32 4094 to half*)
+ %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef
@@ -375,10 +375,10 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
-define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8* byval %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
- %gep = getelementptr inbounds i8, i8* %in, i64 4091
- %load = load i8, i8* %gep
+ %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
+ %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -395,10 +395,10 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
-define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8* byval %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry:
- %gep = getelementptr inbounds i8, i8* %in, i64 4091
- %load = load i8, i8* %gep
+ %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
+ %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -415,9 +415,9 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
-define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8* %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry:
- %load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
+ %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -434,9 +434,9 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
-define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8* %in, i16 %reg) #0 {
+define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry:
- %load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
+ %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -453,9 +453,9 @@ entry:
; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
-define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8* %in, half %reg) #0 {
+define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 {
entry:
- %load = load volatile i8, i8* inttoptr (i32 4094 to i8*)
+ %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half
%build0 = insertelement <2 x half> undef, half %reg, i32 0
@@ -510,12 +510,12 @@ entry:
; GFX9-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094
define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 {
entry:
- %obj0 = alloca [10 x i32], align 4
- %obj1 = alloca [4096 x i16], align 2
- %bc = bitcast [10 x i32]* %obj0 to i32*
- store volatile i32 123, i32* %bc
- %gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025
- %load = load i16, i16* %gep
+ %obj0 = alloca [10 x i32], align 4, addrspace(5)
+ %obj1 = alloca [4096 x i16], align 2, addrspace(5)
+ %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
+ store volatile i32 123, i32 addrspace(5)* %bc
+ %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2025
+ %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
@@ -527,12 +527,12 @@ entry:
; GFX9-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 {
entry:
- %obj0 = alloca [10 x i32], align 4
- %obj1 = alloca [4096 x i8], align 2
- %bc = bitcast [10 x i32]* %obj0 to i32*
- store volatile i32 123, i32* %bc
- %gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
- %load = load i8, i8* %gep
+ %obj0 = alloca [10 x i32], align 4, addrspace(5)
+ %obj1 = alloca [4096 x i8], align 2, addrspace(5)
+ %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
+ store volatile i32 123, i32 addrspace(5)* %bc
+ %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
+ %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -545,12 +545,12 @@ entry:
; GFX9-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 {
entry:
- %obj0 = alloca [10 x i32], align 4
- %obj1 = alloca [4096 x i8], align 2
- %bc = bitcast [10 x i32]* %obj0 to i32*
- store volatile i32 123, i32* %bc
- %gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051
- %load = load i8, i8* %gep
+ %obj0 = alloca [10 x i32], align 4, addrspace(5)
+ %obj1 = alloca [4096 x i8], align 2, addrspace(5)
+ %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
+ store volatile i32 123, i32 addrspace(5)* %bc
+ %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
+ %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
@@ -606,11 +606,11 @@ entry:
; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64
-define <2 x i16> @load_flat_v2i16_split(i16 addrspace(4)* %in) #0 {
+define <2 x i16> @load_flat_v2i16_split(i16* %in) #0 {
entry:
- %gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 1
- %load0 = load volatile i16, i16 addrspace(4)* %in
- %load1 = load volatile i16, i16 addrspace(4)* %gep
+ %gep = getelementptr inbounds i16, i16* %in, i64 1
+ %load0 = load volatile i16, i16* %in
+ %load1 = load volatile i16, i16* %gep
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
@@ -644,11 +644,11 @@ entry:
; GFX9-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:6
; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64
-define <2 x i16> @load_private_v2i16_split(i16* byval %in) #0 {
+define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 {
entry:
- %gep = getelementptr inbounds i16, i16* %in, i32 1
- %load0 = load volatile i16, i16* %in
- %load1 = load volatile i16, i16* %gep
+ %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1
+ %load0 = load volatile i16, i16 addrspace(5)* %in
+ %load1 = load volatile i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
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