diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.pow.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.pow.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll index c4ae652619c..8d1381143ad 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll @@ -5,7 +5,7 @@ ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, -define void @test1(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test1(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = call float @llvm.pow.f32( float %r0, float %r1) @@ -27,7 +27,7 @@ define void @test1(<4 x float> inreg %reg0) #0 { ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, -define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void @@ -36,5 +36,3 @@ define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { declare float @llvm.pow.f32(float ,float ) readonly declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } |
