diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/inline-constraints.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-constraints.ll | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll index 7282e89e85b..3c0bb75a607 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll @@ -26,8 +26,43 @@ entry: ; GCN: s_mov_b32 m0, -1 ; GCN-NOT: s_mov_b32 s{{[0-9]+}}, m0 ; GCN: ; use m0 -define void @inline_sreg_constraint_m0(i32 addrspace(1)* %ptr) { +define void @inline_sreg_constraint_m0() { %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"() tail call void asm sideeffect "; use $0", "s"(i32 %m0) ret void } + +; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32: +; GCN: s_mov_b32 [[REG:s[0-9]+]], 32 +; GCN: ; use [[REG]] +define void @inline_sreg_constraint_imm_i32() { + tail call void asm sideeffect "; use $0", "s"(i32 32) + ret void +} + +; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f32: +; GCN: s_mov_b32 [[REG:s[0-9]+]], 1.0 +; GCN: ; use [[REG]] +define void @inline_sreg_constraint_imm_f32() { + tail call void asm sideeffect "; use $0", "s"(float 1.0) + ret void +} + +; FIXME: Should be able to use s_mov_b64 +; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i64: +; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], -4{{$}} +; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], -1{{$}} +; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} +define void @inline_sreg_constraint_imm_i64() { + tail call void asm sideeffect "; use $0", "s"(i64 -4) + ret void +} + +; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f64: +; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}} +; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}} +; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} +define void @inline_sreg_constraint_imm_f64() { + tail call void asm sideeffect "; use $0", "s"(double 1.0) + ret void +} |
