diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/idot8s.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/idot8s.ll | 703 |
1 files changed, 343 insertions, 360 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll index 3667dfc89bc..c984b657cd7 100644 --- a/llvm/test/CodeGen/AMDGPU/idot8s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll @@ -331,39 +331,38 @@ define amdgpu_kernel void @idot8_acc16(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: s_bfe_i32 s1, s4, 0x40000 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_bfe_i32 s5, s4, 0x40004 -; GFX8-NEXT: s_bfe_i32 s6, s4, 0x40008 ; GFX8-NEXT: s_lshr_b32 s1, s2, 12 -; GFX8-NEXT: s_lshr_b32 s7, s4, 12 -; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40004 -; GFX8-NEXT: s_bfe_i32 s9, s2, 0x40008 -; GFX8-NEXT: v_mov_b32_e32 v4, s6 -; GFX8-NEXT: v_mov_b32_e32 v7, s5 +; GFX8-NEXT: s_lshr_b32 s6, s4, 12 +; GFX8-NEXT: s_bfe_i32 s8, s4, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: s_bfe_i32 s7, s2, 0x40004 ; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s1 -; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s7 -; GFX8-NEXT: v_mul_i32_i24_e32 v4, s9, v4 -; GFX8-NEXT: s_bfe_i32 s10, s4, 0x40010 +; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX8-NEXT: v_mov_b32_e32 v7, s8 +; GFX8-NEXT: s_bfe_i32 s5, s2, 0x40008 +; GFX8-NEXT: s_bfe_i32 s1, s4, 0x40010 ; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 -; GFX8-NEXT: s_bfe_i32 s12, s4, 0x40014 -; GFX8-NEXT: s_bfe_i32 s11, s2, 0x40010 -; GFX8-NEXT: v_mov_b32_e32 v8, s10 -; GFX8-NEXT: s_bfe_i32 s14, s4, 0x40018 -; GFX8-NEXT: s_bfe_i32 s13, s2, 0x40014 -; GFX8-NEXT: v_mov_b32_e32 v9, s12 -; GFX8-NEXT: s_bfe_i32 s15, s2, 0x40018 +; GFX8-NEXT: s_bfe_i32 s8, s4, 0x40014 +; GFX8-NEXT: v_mov_b32_e32 v8, s1 +; GFX8-NEXT: s_bfe_i32 s6, s2, 0x40010 +; GFX8-NEXT: s_bfe_i32 s9, s4, 0x40018 +; GFX8-NEXT: v_mov_b32_e32 v9, s8 +; GFX8-NEXT: s_bfe_i32 s1, s2, 0x40014 +; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40018 ; GFX8-NEXT: s_ashr_i32 s4, s4, 28 -; GFX8-NEXT: v_mov_b32_e32 v10, s14 +; GFX8-NEXT: v_mov_b32_e32 v10, s9 ; GFX8-NEXT: s_ashr_i32 s2, s2, 28 +; GFX8-NEXT: v_mov_b32_e32 v11, s4 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2 -; GFX8-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX8-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s5, v7, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, v5, v6, v2 -; GFX8-NEXT: v_mad_i32_i24 v2, s11, v8, v2 -; GFX8-NEXT: v_mad_i32_i24 v2, s13, v9, v2 -; GFX8-NEXT: v_mad_i32_i24 v2, s15, v10, v2 -; GFX8-NEXT: v_mov_b32_e32 v3, s4 -; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s6, v8, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s1, v9, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s8, v10, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v11, v2 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm ; @@ -382,39 +381,38 @@ define amdgpu_kernel void @idot8_acc16(<8 x i4> addrspace(1)* %src1, ; GFX9-NEXT: s_bfe_i32 s1, s4, 0x40000 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_bfe_i32 s5, s4, 0x40004 -; GFX9-NEXT: s_bfe_i32 s6, s4, 0x40008 ; GFX9-NEXT: s_lshr_b32 s1, s2, 12 -; GFX9-NEXT: s_lshr_b32 s7, s4, 12 -; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40004 -; GFX9-NEXT: s_bfe_i32 s9, s2, 0x40008 -; GFX9-NEXT: v_mov_b32_e32 v4, s6 -; GFX9-NEXT: v_mov_b32_e32 v7, s5 +; GFX9-NEXT: s_lshr_b32 s6, s4, 12 +; GFX9-NEXT: s_bfe_i32 s8, s4, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NEXT: s_bfe_i32 s7, s2, 0x40004 ; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s1 -; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s7 -; GFX9-NEXT: v_mul_i32_i24_e32 v4, s9, v4 -; GFX9-NEXT: s_bfe_i32 s10, s4, 0x40010 +; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX9-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-NEXT: s_bfe_i32 s5, s2, 0x40008 +; GFX9-NEXT: s_bfe_i32 s1, s4, 0x40010 ; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6 -; GFX9-NEXT: s_bfe_i32 s12, s4, 0x40014 -; GFX9-NEXT: s_bfe_i32 s11, s2, 0x40010 -; GFX9-NEXT: v_mov_b32_e32 v8, s10 -; GFX9-NEXT: s_bfe_i32 s14, s4, 0x40018 -; GFX9-NEXT: s_bfe_i32 s13, s2, 0x40014 -; GFX9-NEXT: v_mov_b32_e32 v9, s12 -; GFX9-NEXT: s_bfe_i32 s15, s2, 0x40018 +; GFX9-NEXT: s_bfe_i32 s8, s4, 0x40014 +; GFX9-NEXT: v_mov_b32_e32 v8, s1 +; GFX9-NEXT: s_bfe_i32 s6, s2, 0x40010 +; GFX9-NEXT: s_bfe_i32 s9, s4, 0x40018 +; GFX9-NEXT: v_mov_b32_e32 v9, s8 +; GFX9-NEXT: s_bfe_i32 s1, s2, 0x40014 +; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40018 ; GFX9-NEXT: s_ashr_i32 s4, s4, 28 -; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v10, s9 ; GFX9-NEXT: s_ashr_i32 s2, s2, 28 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_mad_i32_i24 v2, s0, v3, v2 -; GFX9-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s5, v7, v2 ; GFX9-NEXT: v_mad_u32_u24 v2, v5, v6, v2 -; GFX9-NEXT: v_mad_i32_i24 v2, s11, v8, v2 -; GFX9-NEXT: v_mad_i32_i24 v2, s13, v9, v2 -; GFX9-NEXT: v_mad_i32_i24 v2, s15, v10, v2 -; GFX9-NEXT: v_mov_b32_e32 v3, s4 -; GFX9-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s6, v8, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s1, v9, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s8, v10, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s2, v11, v2 ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; @@ -433,39 +431,38 @@ define amdgpu_kernel void @idot8_acc16(<8 x i4> addrspace(1)* %src1, ; GFX9-DL-NEXT: s_bfe_i32 s1, s4, 0x40000 ; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-DL-NEXT: s_bfe_i32 s5, s4, 0x40004 -; GFX9-DL-NEXT: s_bfe_i32 s6, s4, 0x40008 ; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 12 -; GFX9-DL-NEXT: s_lshr_b32 s7, s4, 12 -; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x40004 -; GFX9-DL-NEXT: s_bfe_i32 s9, s2, 0x40008 -; GFX9-DL-NEXT: v_mov_b32_e32 v4, s6 -; GFX9-DL-NEXT: v_mov_b32_e32 v7, s5 +; GFX9-DL-NEXT: s_lshr_b32 s6, s4, 12 +; GFX9-DL-NEXT: s_bfe_i32 s8, s4, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_i32 s7, s2, 0x40004 ; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s1 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s7 -; GFX9-DL-NEXT: v_mul_i32_i24_e32 v4, s9, v4 -; GFX9-DL-NEXT: s_bfe_i32 s10, s4, 0x40010 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-DL-NEXT: s_bfe_i32 s5, s2, 0x40008 +; GFX9-DL-NEXT: s_bfe_i32 s1, s4, 0x40010 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6 -; GFX9-DL-NEXT: s_bfe_i32 s12, s4, 0x40014 -; GFX9-DL-NEXT: s_bfe_i32 s11, s2, 0x40010 -; GFX9-DL-NEXT: v_mov_b32_e32 v8, s10 -; GFX9-DL-NEXT: s_bfe_i32 s14, s4, 0x40018 -; GFX9-DL-NEXT: s_bfe_i32 s13, s2, 0x40014 -; GFX9-DL-NEXT: v_mov_b32_e32 v9, s12 -; GFX9-DL-NEXT: s_bfe_i32 s15, s2, 0x40018 +; GFX9-DL-NEXT: s_bfe_i32 s8, s4, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s1 +; GFX9-DL-NEXT: s_bfe_i32 s6, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_i32 s9, s4, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s8 +; GFX9-DL-NEXT: s_bfe_i32 s1, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x40018 ; GFX9-DL-NEXT: s_ashr_i32 s4, s4, 28 -; GFX9-DL-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-DL-NEXT: v_mov_b32_e32 v10, s9 ; GFX9-DL-NEXT: s_ashr_i32 s2, s2, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v11, s4 ; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s5, v7, v2 ; GFX9-DL-NEXT: v_mad_u32_u24 v2, v5, v6, v2 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s11, v8, v2 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s13, v9, v2 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s15, v10, v2 -; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s6, v8, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s1, v9, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v10, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v11, v2 ; GFX9-DL-NEXT: global_store_short v[0:1], v2, off ; GFX9-DL-NEXT: s_endpgm ; @@ -496,26 +493,25 @@ define amdgpu_kernel void @idot8_acc16(<8 x i4> addrspace(1)* %src1, ; GFX10-DL-NEXT: v_and_b32_e32 v5, v5, v2 ; GFX10-DL-NEXT: s_bfe_i32 s9, s2, 0x40010 ; GFX10-DL-NEXT: s_bfe_i32 s10, s4, 0x40010 -; GFX10-DL-NEXT: v_mul_i32_i24_e64 v6, s1, s8 +; GFX10-DL-NEXT: s_bfe_i32 s11, s2, 0x40014 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v5 -; GFX10-DL-NEXT: s_bfe_i32 s1, s2, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s8, s4, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s11, s2, 0x40018 +; GFX10-DL-NEXT: s_bfe_i32 s12, s4, 0x40014 +; GFX10-DL-NEXT: s_bfe_i32 s13, s2, 0x40018 +; GFX10-DL-NEXT: s_bfe_i32 s14, s4, 0x40018 ; GFX10-DL-NEXT: v_and_b32_e32 v4, v4, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, v5, v2 -; GFX10-DL-NEXT: s_bfe_i32 s12, s4, 0x40018 -; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 28 -; GFX10-DL-NEXT: s_ashr_i32 s4, s4, 28 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_i32_i24 v3, s5, s6, v3 ; GFX10-DL-NEXT: v_mad_i32_i24 v3, s7, s0, v3 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX10-DL-NEXT: s_ashr_i32 s0, s2, 28 +; GFX10-DL-NEXT: v_mad_i32_i24 v3, s1, s8, v3 +; GFX10-DL-NEXT: s_ashr_i32 s1, s4, 28 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v4, v2, v3 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s9, s10, v2 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s8, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s11, s12, v2 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s4, v2 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s13, s14, v2 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, @@ -668,21 +664,20 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: s_bfe_i32 s7, s1, 0x40000 ; GFX8-NEXT: s_lshr_b32 s5, s1, 12 ; GFX8-NEXT: s_bfe_i32 s9, s1, 0x40004 -; GFX8-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX8-NEXT: s_bfe_i32 s6, s0, 0x40000 -; GFX8-NEXT: v_mov_b32_e32 v6, s7 -; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s4 -; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s5 +; GFX8-NEXT: v_mov_b32_e32 v5, s7 +; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s4 +; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s5 +; GFX8-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX8-NEXT: s_bfe_i32 s8, s0, 0x40004 -; GFX8-NEXT: s_bfe_i32 s10, s0, 0x40008 -; GFX8-NEXT: v_mov_b32_e32 v3, s11 -; GFX8-NEXT: v_mov_b32_e32 v7, s9 +; GFX8-NEXT: v_mov_b32_e32 v6, s9 +; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 -; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 -; GFX8-NEXT: v_mul_i32_i24_e32 v3, s10, v3 +; GFX8-NEXT: s_bfe_i32 s10, s0, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v7, s11 ; GFX8-NEXT: s_bfe_i32 s13, s1, 0x40010 +; GFX8-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX8-NEXT: v_and_b32_e32 v4, s2, v4 -; GFX8-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX8-NEXT: s_bfe_i32 s15, s1, 0x40014 ; GFX8-NEXT: s_bfe_i32 s12, s0, 0x40010 ; GFX8-NEXT: v_mov_b32_e32 v8, s13 @@ -694,10 +689,10 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: v_mov_b32_e32 v10, s17 ; GFX8-NEXT: s_ashr_i32 s0, s0, 28 ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mad_i32_i24 v2, s6, v6, v2 -; GFX8-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX8-NEXT: v_mad_u32_u24 v2, v4, v5, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s8, v6, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s10, v7, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s12, v8, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s14, v9, v2 ; GFX8-NEXT: v_mad_i32_i24 v2, s16, v10, v2 @@ -722,21 +717,20 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX9-NEXT: s_bfe_i32 s7, s1, 0x40000 ; GFX9-NEXT: s_lshr_b32 s5, s1, 12 ; GFX9-NEXT: s_bfe_i32 s9, s1, 0x40004 -; GFX9-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX9-NEXT: s_bfe_i32 s6, s0, 0x40000 -; GFX9-NEXT: v_mov_b32_e32 v6, s7 -; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s4 -; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s5 +; GFX9-NEXT: v_mov_b32_e32 v5, s7 +; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s4 +; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s5 +; GFX9-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX9-NEXT: s_bfe_i32 s8, s0, 0x40004 -; GFX9-NEXT: s_bfe_i32 s10, s0, 0x40008 -; GFX9-NEXT: v_mov_b32_e32 v3, s11 -; GFX9-NEXT: v_mov_b32_e32 v7, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s9 +; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 -; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5 -; GFX9-NEXT: v_mul_i32_i24_e32 v3, s10, v3 +; GFX9-NEXT: s_bfe_i32 s10, s0, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 ; GFX9-NEXT: s_bfe_i32 s13, s1, 0x40010 +; GFX9-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_and_b32_e32 v4, s2, v4 -; GFX9-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-NEXT: s_bfe_i32 s15, s1, 0x40014 ; GFX9-NEXT: s_bfe_i32 s12, s0, 0x40010 ; GFX9-NEXT: v_mov_b32_e32 v8, s13 @@ -748,10 +742,10 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX9-NEXT: v_mov_b32_e32 v10, s17 ; GFX9-NEXT: s_ashr_i32 s0, s0, 28 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mad_i32_i24 v2, s6, v6, v2 -; GFX9-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX9-NEXT: v_mad_u32_u24 v2, v4, v5, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s8, v6, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s10, v7, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s12, v8, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s14, v9, v2 ; GFX9-NEXT: v_mad_i32_i24 v2, s16, v10, v2 @@ -776,21 +770,20 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX9-DL-NEXT: s_bfe_i32 s7, s1, 0x40000 ; GFX9-DL-NEXT: s_lshr_b32 s5, s1, 12 ; GFX9-DL-NEXT: s_bfe_i32 s9, s1, 0x40004 -; GFX9-DL-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX9-DL-NEXT: s_bfe_i32 s6, s0, 0x40000 -; GFX9-DL-NEXT: v_mov_b32_e32 v6, s7 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s4 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s5 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s7 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s5 +; GFX9-DL-NEXT: s_bfe_i32 s11, s1, 0x40008 ; GFX9-DL-NEXT: s_bfe_i32 s8, s0, 0x40004 -; GFX9-DL-NEXT: s_bfe_i32 s10, s0, 0x40008 -; GFX9-DL-NEXT: v_mov_b32_e32 v3, s11 -; GFX9-DL-NEXT: v_mov_b32_e32 v7, s9 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 -; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5 -; GFX9-DL-NEXT: v_mul_i32_i24_e32 v3, s10, v3 +; GFX9-DL-NEXT: s_bfe_i32 s10, s0, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s11 ; GFX9-DL-NEXT: s_bfe_i32 s13, s1, 0x40010 +; GFX9-DL-NEXT: v_and_b32_e32 v3, s2, v3 ; GFX9-DL-NEXT: v_and_b32_e32 v4, s2, v4 -; GFX9-DL-NEXT: v_and_b32_e32 v5, s2, v5 ; GFX9-DL-NEXT: s_bfe_i32 s15, s1, 0x40014 ; GFX9-DL-NEXT: s_bfe_i32 s12, s0, 0x40010 ; GFX9-DL-NEXT: v_mov_b32_e32 v8, s13 @@ -802,10 +795,10 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX9-DL-NEXT: v_mov_b32_e32 v10, s17 ; GFX9-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX9-DL-NEXT: s_waitcnt vmcnt(0) -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s6, v6, v2 -; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v7, v2 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX9-DL-NEXT: v_mad_u32_u24 v2, v4, v5, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v6, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s10, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s12, v8, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s14, v9, v2 ; GFX9-DL-NEXT: v_mad_i32_i24 v2, s16, v10, v2 @@ -842,26 +835,25 @@ define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, ; GFX10-DL-NEXT: v_and_b32_e32 v2, v5, v2 ; GFX10-DL-NEXT: s_bfe_i32 s10, s4, 0x40010 ; GFX10-DL-NEXT: s_bfe_i32 s11, s5, 0x40010 -; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s1, s9 +; GFX10-DL-NEXT: s_bfe_i32 s12, s4, 0x40014 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v2, 12, v2 -; GFX10-DL-NEXT: s_bfe_i32 s1, s4, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s9, s5, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s12, s4, 0x40018 +; GFX10-DL-NEXT: s_bfe_i32 s13, s5, 0x40014 +; GFX10-DL-NEXT: s_bfe_i32 s14, s4, 0x40018 +; GFX10-DL-NEXT: s_bfe_i32 s15, s5, 0x40018 ; GFX10-DL-NEXT: v_and_b32_sdwa v4, v4, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_and_b32_sdwa v2, v2, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX10-DL-NEXT: s_bfe_i32 s2, s5, 0x40018 -; GFX10-DL-NEXT: s_ashr_i32 s4, s4, 28 -; GFX10-DL-NEXT: s_ashr_i32 s5, s5, 28 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_i32_i24 v3, s6, s7, v3 ; GFX10-DL-NEXT: v_mad_i32_i24 v3, s8, s0, v3 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX10-DL-NEXT: s_ashr_i32 s0, s4, 28 +; GFX10-DL-NEXT: v_mad_i32_i24 v3, s1, s9, v3 +; GFX10-DL-NEXT: s_ashr_i32 s1, s5, 28 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v4, v2, v3 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s10, s11, v2 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s9, v2 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s12, s2, v2 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s12, s13, v2 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s14, s15, v2 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, @@ -1582,69 +1574,57 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s6, -1 -; GFX7-NEXT: s_mov_b32 s0, 0xffff +; GFX7-NEXT: s_mov_b32 s2, 0xffff ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_load_dword s1, s[8:9], 0x0 +; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0 ; GFX7-NEXT: buffer_load_ushort v0, off, s[4:7], 0 -; GFX7-NEXT: s_load_dword s2, s[10:11], 0x0 +; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_bfe_i32 s8, s1, 0x40010 -; GFX7-NEXT: s_bfe_i32 s9, s1, 0x40014 -; GFX7-NEXT: s_bfe_i32 s15, s2, 0x40010 -; GFX7-NEXT: s_bfe_i32 s16, s2, 0x40014 -; GFX7-NEXT: s_bfe_i32 s17, s2, 0x40018 -; GFX7-NEXT: s_ashr_i32 s18, s2, 28 -; GFX7-NEXT: s_bfe_i32 s19, s2, 0x40000 -; GFX7-NEXT: s_bfe_i32 s20, s2, 0x40004 -; GFX7-NEXT: s_bfe_i32 s21, s2, 0x40008 -; GFX7-NEXT: s_bfe_i32 s2, s2, 0x4000c -; GFX7-NEXT: s_bfe_i32 s10, s1, 0x40018 -; GFX7-NEXT: s_ashr_i32 s11, s1, 28 -; GFX7-NEXT: s_bfe_i32 s12, s1, 0x40000 +; GFX7-NEXT: s_ashr_i32 s8, s0, 28 +; GFX7-NEXT: s_bfe_i32 s9, s0, 0x40018 +; GFX7-NEXT: s_bfe_i32 s16, s1, 0x40018 +; GFX7-NEXT: s_bfe_i32 s17, s1, 0x40014 +; GFX7-NEXT: s_bfe_i32 s18, s1, 0x40010 +; GFX7-NEXT: s_bfe_i32 s19, s1, 0x40000 +; GFX7-NEXT: s_bfe_i32 s20, s1, 0x40004 +; GFX7-NEXT: s_bfe_i32 s21, s1, 0x40008 +; GFX7-NEXT: s_ashr_i32 s15, s1, 28 +; GFX7-NEXT: s_bfe_i32 s1, s1, 0x4000c +; GFX7-NEXT: s_bfe_i32 s10, s0, 0x40014 +; GFX7-NEXT: s_bfe_i32 s11, s0, 0x40010 +; GFX7-NEXT: s_bfe_i32 s12, s0, 0x40000 ; GFX7-NEXT: v_mov_b32_e32 v4, s19 -; GFX7-NEXT: s_bfe_i32 s13, s1, 0x40004 +; GFX7-NEXT: s_bfe_i32 s13, s0, 0x40004 ; GFX7-NEXT: v_mov_b32_e32 v3, s20 -; GFX7-NEXT: s_bfe_i32 s14, s1, 0x40008 +; GFX7-NEXT: s_bfe_i32 s14, s0, 0x40008 ; GFX7-NEXT: v_mov_b32_e32 v2, s21 -; GFX7-NEXT: s_bfe_i32 s1, s1, 0x4000c -; GFX7-NEXT: v_mov_b32_e32 v1, s2 -; GFX7-NEXT: v_mov_b32_e32 v5, s18 -; GFX7-NEXT: v_mov_b32_e32 v6, s17 -; GFX7-NEXT: v_mul_i32_i24_e32 v1, s1, v1 -; GFX7-NEXT: v_mul_i32_i24_e32 v2, s14, v2 +; GFX7-NEXT: s_bfe_i32 s0, s0, 0x4000c +; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: v_mul_i32_i24_e32 v1, s0, v1 +; GFX7-NEXT: v_mul_i32_i24_e32 v8, s14, v2 ; GFX7-NEXT: v_mul_i32_i24_e32 v3, s13, v3 ; GFX7-NEXT: v_mul_i32_i24_e32 v4, s12, v4 -; GFX7-NEXT: v_mul_i32_i24_e32 v5, s11, v5 -; GFX7-NEXT: v_mul_i32_i24_e32 v6, s10, v6 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX7-NEXT: v_and_b32_e32 v2, s0, v2 +; GFX7-NEXT: v_and_b32_e32 v8, s2, v8 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_and_b32_e32 v4, s0, v4 -; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 -; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 -; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX7-NEXT: v_and_b32_e32 v6, s0, v6 +; GFX7-NEXT: v_and_b32_e32 v4, s2, v4 +; GFX7-NEXT: v_or_b32_e32 v3, v4, v3 +; GFX7-NEXT: v_or_b32_e32 v1, v8, v1 +; GFX7-NEXT: v_alignbit_b32 v4, v1, v3, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_mov_b32_e32 v5, s18 +; GFX7-NEXT: v_mov_b32_e32 v6, s17 ; GFX7-NEXT: v_mov_b32_e32 v7, s16 -; GFX7-NEXT: v_mov_b32_e32 v8, s15 -; GFX7-NEXT: v_or_b32_e32 v3, v6, v5 -; GFX7-NEXT: v_alignbit_b32 v5, v1, v2, 16 -; GFX7-NEXT: v_mul_i32_i24_e32 v7, s9, v7 -; GFX7-NEXT: v_mul_i32_i24_e32 v8, s8, v8 -; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX7-NEXT: v_and_b32_e32 v8, s0, v8 -; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GFX7-NEXT: v_or_b32_e32 v4, v8, v7 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v4 -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v3 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v8, v0 +; GFX7-NEXT: v_mad_i32_i24 v0, s14, v2, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_mad_i32_i24 v0, s11, v5, v0 +; GFX7-NEXT: v_mad_i32_i24 v0, s10, v6, v0 +; GFX7-NEXT: v_mad_i32_i24 v0, s9, v7, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s15 +; GFX7-NEXT: v_mad_i32_i24 v0, s8, v1, v0 ; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0 ; GFX7-NEXT: s_endpgm ; @@ -1662,26 +1642,25 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s2 ; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s4 ; GFX8-NEXT: s_lshr_b32 s0, s2, 4 -; GFX8-NEXT: s_lshr_b32 s1, s2, 8 -; GFX8-NEXT: s_lshr_b32 s5, s4, 4 +; GFX8-NEXT: s_lshr_b32 s1, s4, 4 +; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s1 +; GFX8-NEXT: s_lshr_b32 s5, s2, 8 ; GFX8-NEXT: s_lshr_b32 s6, s4, 8 -; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s1 -; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s0 -; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s6 -; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 ; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 ; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s6 ; GFX8-NEXT: s_lshr_b32 s0, s2, 12 ; GFX8-NEXT: s_lshr_b32 s1, s4, 12 -; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 -; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 -; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s0 ; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s1 ; GFX8-NEXT: s_lshr_b32 s5, s2, 16 ; GFX8-NEXT: s_lshr_b32 s6, s4, 16 -; GFX8-NEXT: v_mul_u32_u24_e32 v5, v5, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 ; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s5 ; GFX8-NEXT: v_lshlrev_b16_e64 v12, 12, s6 ; GFX8-NEXT: s_lshr_b32 s0, s2, 20 @@ -1695,26 +1674,26 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 ; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 ; GFX8-NEXT: v_lshlrev_b16_e64 v15, 12, s5 -; GFX8-NEXT: v_lshlrev_b16_e64 v17, 12, s6 +; GFX8-NEXT: v_lshlrev_b16_e64 v16, 12, s6 ; GFX8-NEXT: s_lshr_b32 s0, s2, 28 ; GFX8-NEXT: s_lshr_b32 s1, s4, 28 ; GFX8-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX8-NEXT: v_ashrrev_i16_e32 v14, 12, v14 -; GFX8-NEXT: v_lshlrev_b16_e64 v16, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v17, 12, s0 ; GFX8-NEXT: v_lshlrev_b16_e64 v18, 12, s1 ; GFX8-NEXT: v_ashrrev_i16_e32 v15, 12, v15 -; GFX8-NEXT: v_ashrrev_i16_e32 v17, 12, v17 ; GFX8-NEXT: v_ashrrev_i16_e32 v16, 12, v16 +; GFX8-NEXT: v_ashrrev_i16_e32 v17, 12, v17 ; GFX8-NEXT: v_ashrrev_i16_e32 v18, 12, v18 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 -; GFX8-NEXT: v_mad_u32_u24 v2, v6, v8, v2 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX8-NEXT: v_mad_u32_u24 v2, v5, v6, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v7, v8, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, v9, v10, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, v11, v12, v2 ; GFX8-NEXT: v_mad_u32_u24 v2, v13, v14, v2 -; GFX8-NEXT: v_mad_u32_u24 v2, v15, v17, v2 -; GFX8-NEXT: v_mad_u32_u24 v2, v16, v18, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v15, v16, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v17, v18, v2 ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm ; @@ -1776,7 +1755,7 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 @@ -1843,7 +1822,7 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 @@ -1911,7 +1890,7 @@ define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v5 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 @@ -1994,7 +1973,7 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX7-NEXT: v_mul_i32_i24_e32 v1, s2, v1 ; GFX7-NEXT: v_mul_i32_i24_e32 v2, s15, v2 ; GFX7-NEXT: v_mul_i32_i24_e32 v3, s14, v3 -; GFX7-NEXT: v_mul_i32_i24_e32 v4, s13, v4 +; GFX7-NEXT: v_mul_i32_i24_e32 v9, s13, v4 ; GFX7-NEXT: v_mul_i32_i24_e32 v5, s12, v5 ; GFX7-NEXT: v_mul_i32_i24_e32 v6, s11, v6 ; GFX7-NEXT: v_mul_i32_i24_e32 v7, s10, v7 @@ -2002,36 +1981,36 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX7-NEXT: v_and_b32_e32 v2, s0, v2 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX7-NEXT: v_and_b32_e32 v4, s0, v4 +; GFX7-NEXT: v_and_b32_e32 v9, s0, v9 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5 ; GFX7-NEXT: v_and_b32_e32 v6, s0, v6 ; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7 ; GFX7-NEXT: v_and_b32_e32 v8, s0, v8 ; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 -; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_or_b32_e32 v2, v9, v3 ; GFX7-NEXT: v_or_b32_e32 v3, v6, v5 -; GFX7-NEXT: v_or_b32_e32 v4, v8, v7 +; GFX7-NEXT: v_or_b32_e32 v5, v8, v7 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX7-NEXT: v_and_b32_e32 v2, s1, v2 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX7-NEXT: v_and_b32_e32 v4, s1, v4 +; GFX7-NEXT: v_and_b32_e32 v5, s1, v5 ; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 -; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_or_b32_e32 v2, v5, v3 ; GFX7-NEXT: v_alignbit_b32 v3, v1, v2, 8 -; GFX7-NEXT: v_alignbit_b32 v4, v1, v2, 16 -; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v6, 8, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v1 +; GFX7-NEXT: v_alignbit_b32 v5, v1, v2, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 24, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v7, 8, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v1 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v5, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v6, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v7, v0 -; GFX7-NEXT: v_add_i32_e32 v0, vcc, v8, v0 +; GFX7-NEXT: v_mad_i32_i24 v0, s13, v4, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v8 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0 ; GFX7-NEXT: s_endpgm ; @@ -2068,55 +2047,56 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 -; GFX8-NEXT: v_mul_u32_u24_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX8-NEXT: v_mul_u32_u24_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX8-NEXT: v_mul_u32_u24_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v6, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: s_lshr_b32 s5, s4, 20 +; GFX8-NEXT: s_lshr_b32 s6, s4, 16 ; GFX8-NEXT: s_lshr_b32 s0, s2, 20 +; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v6, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX8-NEXT: s_lshr_b32 s1, s2, 16 -; GFX8-NEXT: s_lshr_b32 s5, s2, 28 -; GFX8-NEXT: s_lshr_b32 s2, s2, 24 -; GFX8-NEXT: s_lshr_b32 s6, s4, 20 -; GFX8-NEXT: s_lshr_b32 s7, s4, 16 +; GFX8-NEXT: v_mul_u32_u24_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: s_lshr_b32 s7, s2, 28 ; GFX8-NEXT: s_lshr_b32 s8, s4, 28 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s1 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v13, 12, s6 +; GFX8-NEXT: v_lshlrev_b16_e64 v14, 12, s5 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 ; GFX8-NEXT: s_lshr_b32 s4, s4, 24 ; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s2 -; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 -; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s1 -; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s7 ; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s4 ; GFX8-NEXT: v_lshlrev_b16_e64 v12, 12, s8 -; GFX8-NEXT: v_lshlrev_b16_e64 v13, 12, s7 -; GFX8-NEXT: v_lshlrev_b16_e64 v14, 12, s6 -; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 -; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 -; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 -; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX8-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX8-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 ; GFX8-NEXT: v_ashrrev_i16_e32 v14, 12, v14 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v3 -; GFX8-NEXT: v_mul_u32_u24_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX8-NEXT: v_mul_u32_u24_sdwa v8, v8, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 ; GFX8-NEXT: v_mul_u32_u24_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX8-NEXT: v_mul_u32_u24_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 8, v3 ; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_mul_u32_u24_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v8, v8, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX8-NEXT: v_or_b32_sdwa v4, v9, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 8, v4 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v9 +; GFX8-NEXT: v_or_b32_e32 v5, v4, v7 +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 8, v5 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v2 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v6, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v7, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD ; GFX8-NEXT: flat_store_byte v[0:1], v2 ; GFX8-NEXT: s_endpgm ; @@ -2153,55 +2133,56 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-NEXT: s_lshr_b32 s5, s4, 20 +; GFX9-NEXT: s_lshr_b32 s6, s4, 16 +; GFX9-NEXT: s_lshr_b32 s1, s2, 16 ; GFX9-NEXT: v_mul_lo_u16_e32 v6, v6, v10 ; GFX9-NEXT: v_mul_lo_u16_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-NEXT: v_mul_lo_u16_e32 v3, v3, v7 -; GFX9-NEXT: s_lshr_b32 s0, s2, 20 -; GFX9-NEXT: s_lshr_b32 s1, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s2, 28 -; GFX9-NEXT: s_lshr_b32 s2, s2, 24 -; GFX9-NEXT: s_lshr_b32 s6, s4, 20 -; GFX9-NEXT: s_lshr_b32 s7, s4, 16 +; GFX9-NEXT: s_lshr_b32 s7, s2, 28 ; GFX9-NEXT: s_lshr_b32 s8, s4, 28 +; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v14, 12, s6 +; GFX9-NEXT: v_lshlrev_b16_e64 v15, 12, s5 +; GFX9-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-NEXT: s_lshr_b32 s4, s4, 24 ; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s2 +; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s7 +; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s4 +; GFX9-NEXT: v_lshlrev_b16_e64 v13, 12, s8 ; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s2 -; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s5 -; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s1 -; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s0 -; GFX9-NEXT: v_lshlrev_b16_e64 v13, 12, s4 -; GFX9-NEXT: v_lshlrev_b16_e64 v14, 12, s8 -; GFX9-NEXT: v_lshlrev_b16_e64 v15, 12, s7 -; GFX9-NEXT: v_lshlrev_b16_e64 v16, 12, s6 -; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 -; GFX9-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 ; GFX9-NEXT: v_ashrrev_i16_e32 v14, 12, v14 ; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11 ; GFX9-NEXT: v_ashrrev_i16_e32 v15, 12, v15 +; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8 ; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12 -; GFX9-NEXT: v_ashrrev_i16_e32 v16, 12, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v3 -; GFX9-NEXT: v_mul_lo_u16_sdwa v12, v12, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX9-NEXT: v_mul_lo_u16_e32 v11, v11, v15 -; GFX9-NEXT: v_mul_lo_u16_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX9-NEXT: v_mul_lo_u16_e32 v9, v9, v13 -; GFX9-NEXT: v_or_b32_sdwa v7, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v8, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v4, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX9-NEXT: v_mul_lo_u16_sdwa v11, v11, v15 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_e32 v10, v10, v14 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v7, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_sdwa v9, v9, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_e32 v8, v8, v12 +; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v7 +; GFX9-NEXT: v_or_b32_e32 v5, v4, v8 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v4 +; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; @@ -2238,55 +2219,56 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-DL-NEXT: s_lshr_b32 s5, s4, 20 +; GFX9-DL-NEXT: s_lshr_b32 s6, s4, 16 +; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 16 ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v6, v6, v10 ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, v3, v7 -; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 20 -; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 16 -; GFX9-DL-NEXT: s_lshr_b32 s5, s2, 28 -; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 -; GFX9-DL-NEXT: s_lshr_b32 s6, s4, 20 -; GFX9-DL-NEXT: s_lshr_b32 s7, s4, 16 +; GFX9-DL-NEXT: s_lshr_b32 s7, s2, 28 ; GFX9-DL-NEXT: s_lshr_b32 s8, s4, 28 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s6 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s5 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 24 ; GFX9-DL-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s2 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s7 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s8 ; GFX9-DL-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s2 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s5 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s1 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s0 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s4 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s8 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s7 -; GFX9-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s6 -; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 -; GFX9-DL-NEXT: v_ashrrev_i16_e32 v13, 12, v13 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v14, 12, v14 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v15, 12, v15 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8 ; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12 -; GFX9-DL-NEXT: v_ashrrev_i16_e32 v16, 12, v16 -; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 -; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v12, v12, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX9-DL-NEXT: v_mul_lo_u16_e32 v11, v11, v15 -; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, v9, v13 -; GFX9-DL-NEXT: v_or_b32_sdwa v7, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-DL-NEXT: v_or_b32_sdwa v8, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-DL-NEXT: v_or_b32_sdwa v4, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v11, v11, v15 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v10, v10, v14 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v3 +; GFX9-DL-NEXT: v_or_b32_sdwa v7, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v9, v9, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v8, v8, v12 +; GFX9-DL-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xffff, v7 +; GFX9-DL-NEXT: v_or_b32_e32 v5, v4, v8 ; GFX9-DL-NEXT: s_waitcnt vmcnt(0) ; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 -; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v5 ; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX9-DL-NEXT: s_endpgm ; @@ -2332,86 +2314,87 @@ define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v9 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v10 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v11 +; GFX10-DL-NEXT: s_lshr_b32 s0, s4, 16 +; GFX10-DL-NEXT: s_lshr_b32 s1, s4, 20 +; GFX10-DL-NEXT: s_lshr_b32 s7, s5, 20 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v15, 12, v6 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7 -; GFX10-DL-NEXT: s_lshr_b32 s1, s4, 20 -; GFX10-DL-NEXT: s_lshr_b32 s6, s4, 24 -; GFX10-DL-NEXT: s_lshr_b32 s0, s4, 16 +; GFX10-DL-NEXT: s_lshr_b32 s6, s5, 16 +; GFX10-DL-NEXT: s_lshr_b32 s8, s4, 24 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s1 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s0 ; GFX10-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GFX10-DL-NEXT: s_lshr_b32 s8, s5, 20 ; GFX10-DL-NEXT: s_lshr_b32 s9, s5, 24 -; GFX10-DL-NEXT: s_lshr_b32 s7, s5, 16 ; GFX10-DL-NEXT: s_lshr_b32 s5, s5, 28 -; GFX10-DL-NEXT: v_and_b32_e32 v23, v15, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v27, v15, v2 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s6 ; GFX10-DL-NEXT: v_and_b32_e32 v10, v19, v2 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v23, 12, s7 ; GFX10-DL-NEXT: v_and_b32_e32 v5, v5, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v8, v8, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v4, v4, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v9, v9, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v22, v7, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v11, v11, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v15, v15, v2 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v8 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, v4, v9 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s6 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v22, v11 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s0 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v31, 12, s8 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v23, v23, v10 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v27, 12, s1 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s5 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v17, 12, s9 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v19, 12, s7 -; GFX10-DL-NEXT: v_and_b32_e32 v8, v12, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v9, v13, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v11, v15, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v12, v16, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v13, v17, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v15, v19, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v10, v27, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v14, v31, v2 -; GFX10-DL-NEXT: v_and_b32_sdwa v6, v23, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v17, 12, s8 +; GFX10-DL-NEXT: v_and_b32_e32 v13, v13, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v14, v23, v2 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v23, v27, v10 +; GFX10-DL-NEXT: v_and_b32_e32 v12, v12, v2 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v31, 12, s5 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v19, 12, s9 +; GFX10-DL-NEXT: v_and_b32_e32 v8, v16, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v9, v17, v2 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v27, 12, v12 +; GFX10-DL-NEXT: v_and_b32_e32 v12, v31, v2 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v15, 12, v15 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v13 +; GFX10-DL-NEXT: v_and_b32_e32 v13, v19, v2 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v14 ; GFX10-DL-NEXT: v_and_b32_sdwa v7, v7, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX10-DL-NEXT: v_and_b32_sdwa v6, v23, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-DL-NEXT: v_and_b32_sdwa v4, v4, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_and_b32_sdwa v5, v5, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v9 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v12 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v13, 12, v13 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 12, v8 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v9 -; GFX10-DL-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-DL-NEXT: v_and_b32_e32 v10, v27, v2 ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v10 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v15, 12, v15 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v11 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v23, 12, v14 -; GFX10-DL-NEXT: v_and_b32_e32 v5, v8, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v7, v9, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v13, v13, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v9, v11, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v12, v12, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v5, v19, v2 +; GFX10-DL-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v13, 12, v13 +; GFX10-DL-NEXT: v_and_b32_e32 v14, v11, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v15, v15, v2 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v10, v5 ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX10-DL-NEXT: v_and_b32_e32 v10, v15, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v8, v19, v2 -; GFX10-DL-NEXT: v_and_b32_e32 v11, v23, v2 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v7, v13 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v12 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, v9, v10 +; GFX10-DL-NEXT: v_and_b32_e32 v23, v8, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v9, v9, v2 +; GFX10-DL-NEXT: v_and_b32_e32 v7, v13, v2 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v11, v14, v15 +; GFX10-DL-NEXT: v_and_b32_e32 v12, v12, v2 +; GFX10-DL-NEXT: v_and_b32_sdwa v5, v5, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, v9, v7 +; GFX10-DL-NEXT: v_and_b32_sdwa v8, v11, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v23, v12 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v4 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v8, v8, v11 -; GFX10-DL-NEXT: v_and_b32_sdwa v7, v7, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX10-DL-NEXT: v_and_b32_sdwa v6, v6, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX10-DL-NEXT: v_and_b32_sdwa v8, v8, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX10-DL-NEXT: v_and_b32_sdwa v2, v5, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX10-DL-NEXT: v_or_b32_sdwa v5, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GFX10-DL-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GFX10-DL-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX10-DL-NEXT: v_and_b32_sdwa v11, v6, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX10-DL-NEXT: v_or_b32_sdwa v5, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-DL-NEXT: v_and_b32_sdwa v2, v7, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX10-DL-NEXT: v_or_b32_sdwa v2, v11, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-DL-NEXT: v_or_b32_e32 v2, v5, v2 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v3, v4, v3 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v3, v3, v9 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v2 -; GFX10-DL-NEXT: v_add_nc_u32_e32 v3, v3, v2 +; GFX10-DL-NEXT: v_add_nc_u32_e32 v3, v3, v5 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v3, v3, v4 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 |
