diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir b/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir new file mode 100644 index 00000000000..4a858c0d744 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir @@ -0,0 +1,51 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck %s + +# The strange block ordering visits the use before the def. +--- +name: inserted_cmp_operand_class_rpo +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; CHECK-LABEL: name: inserted_cmp_operand_class_rpo + ; CHECK: bb.0: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: S_BRANCH %bb.3 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY %1 + ; CHECK: bb.2: + ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]] + ; CHECK: S_ENDPGM 0 + ; CHECK: bb.3: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 + ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MOV_B32_e32_1]], killed [[S_MOV_B32_]], implicit $exec + ; CHECK: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[V_CMP_EQ_U32_e64_]] + ; CHECK: S_BRANCH %bb.1 + bb.0: + successors: %bb.3 + + S_BRANCH %bb.3 + + bb.1: + successors: %bb.2 + + %0:vreg_1 = COPY %1 + + bb.2: + %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %3:sreg_64_xexec = COPY %0 + S_ENDPGM 0 + + bb.3: + successors: %bb.1 + + %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %5:sreg_32_xm0 = S_MOV_B32 0 + %6:sreg_64 = V_CMP_EQ_U32_e64 killed %4, killed %5, implicit $exec + %1:vreg_1 = COPY %6 + S_BRANCH %bb.1 |

