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-rw-r--r--llvm/test/CodeGen/AArch64/sadd_sat.ll45
-rw-r--r--llvm/test/CodeGen/AArch64/sadd_sat_vec.ll109
-rw-r--r--llvm/test/CodeGen/AArch64/ssub_sat.ll45
-rw-r--r--llvm/test/CodeGen/AArch64/ssub_sat_vec.ll109
-rw-r--r--llvm/test/CodeGen/AArch64/uadd_sat.ll24
-rw-r--r--llvm/test/CodeGen/AArch64/uadd_sat_vec.ll67
-rw-r--r--llvm/test/CodeGen/AArch64/usub_sat.ll21
-rw-r--r--llvm/test/CodeGen/AArch64/usub_sat_vec.ll15
8 files changed, 163 insertions, 272 deletions
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat.ll b/llvm/test/CodeGen/AArch64/sadd_sat.ll
index 9651796ff93..7cbf4e3321a 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat.ll
@@ -39,14 +39,13 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: func16:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #16
-; CHECK-NEXT: adds w10, w8, w1, lsl #16
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: adds w8, w8, w1, lsl #16
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: mov w9, #32767
+; CHECK-NEXT: cmp w8, w9
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT: mov w9, #-32768
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -55,14 +54,13 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #24
-; CHECK-NEXT: adds w10, w8, w1, lsl #24
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: adds w8, w8, w1, lsl #24
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #24
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: mov w9, #127
+; CHECK-NEXT: cmp w8, #127 // =127
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #128 // =128
+; CHECK-NEXT: mov w9, #-128
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -71,14 +69,13 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #28
-; CHECK-NEXT: adds w10, w8, w1, lsl #28
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: adds w8, w8, w1, lsl #28
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: mov w9, #7
+; CHECK-NEXT: cmp w8, #7 // =7
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #8 // =8
+; CHECK-NEXT: mov w9, #-8
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 5a2a24ee9c8..7c713c62d07 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -236,30 +236,23 @@ define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
; CHECK-NEXT: ldrb w11, [x1, #1]
-; CHECK-NEXT: ldrb w12, [x0, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: ldrb w8, [x1, #2]
; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrb w8, [x0, #2]
+; CHECK-NEXT: ldrb w9, [x1, #2]
; CHECK-NEXT: mov v0.h[1], w10
-; CHECK-NEXT: ldrb w9, [x0, #3]
-; CHECK-NEXT: ldrb w10, [x1, #3]
; CHECK-NEXT: mov v1.h[1], w11
-; CHECK-NEXT: mov v0.h[2], w12
-; CHECK-NEXT: mov v1.h[2], w8
-; CHECK-NEXT: mov v0.h[3], w9
-; CHECK-NEXT: mov v1.h[3], w10
-; CHECK-NEXT: shl v1.4h, v1.4h, #8
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: add v3.4h, v0.4h, v1.4h
-; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
-; CHECK-NEXT: mvni v2.4h, #128, lsl #8
-; CHECK-NEXT: cmlt v1.4h, v1.4h, #0
-; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
-; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
-; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-NEXT: ldrb w10, [x0, #3]
+; CHECK-NEXT: ldrb w11, [x1, #3]
+; CHECK-NEXT: mov v0.h[2], w8
+; CHECK-NEXT: mov v1.h[2], w9
+; CHECK-NEXT: mov v0.h[3], w10
+; CHECK-NEXT: mov v1.h[3], w11
+; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: movi v1.4h, #127
+; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: mvni v1.4h, #127
+; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret
@@ -278,21 +271,14 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ldrb w10, [x0, #1]
; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s2, w9
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: mov v2.s[1], w11
-; CHECK-NEXT: shl v2.2s, v2.2s, #24
-; CHECK-NEXT: shl v0.2s, v0.2s, #24
-; CHECK-NEXT: add v3.2s, v0.2s, v2.2s
-; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
-; CHECK-NEXT: mvni v1.2s, #128, lsl #24
-; CHECK-NEXT: cmlt v2.2s, v2.2s, #0
-; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
-; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
-; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
-; CHECK-NEXT: ushr v0.2s, v0.2s, #24
+; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: movi v1.2s, #127
+; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mvni v1.2s, #127
+; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
@@ -336,21 +322,14 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ldrh w10, [x0, #2]
; CHECK-NEXT: ldrh w11, [x1, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s2, w9
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: mov v2.s[1], w11
-; CHECK-NEXT: shl v2.2s, v2.2s, #16
-; CHECK-NEXT: shl v0.2s, v0.2s, #16
-; CHECK-NEXT: add v3.2s, v0.2s, v2.2s
-; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
-; CHECK-NEXT: mvni v1.2s, #128, lsl #24
-; CHECK-NEXT: cmlt v2.2s, v2.2s, #0
-; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
-; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
-; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
-; CHECK-NEXT: ushr v0.2s, v0.2s, #16
+; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: movi v1.2s, #127, msl #8
+; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
@@ -462,18 +441,11 @@ define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #4
-; CHECK-NEXT: shl v0.16b, v0.16b, #4
-; CHECK-NEXT: add v3.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
-; CHECK-NEXT: movi v2.16b, #127
-; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
-; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
-; CHECK-NEXT: mvn v5.16b, v4.16b
-; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: sshr v0.16b, v0.16b, #4
+; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.16b, #7
+; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.16b, #248
+; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z
@@ -482,18 +454,11 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: add v3.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
-; CHECK-NEXT: movi v2.16b, #127
-; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
-; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
-; CHECK-NEXT: mvn v5.16b, v4.16b
-; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: sshr v0.16b, v0.16b, #7
+; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat.ll b/llvm/test/CodeGen/AArch64/ssub_sat.ll
index 0fbe3c4a71c..f934c8d3b23 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat.ll
@@ -39,14 +39,13 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: func16:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #16
-; CHECK-NEXT: subs w10, w8, w1, lsl #16
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: subs w8, w8, w1, lsl #16
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: sub w8, w0, w1
+; CHECK-NEXT: mov w9, #32767
+; CHECK-NEXT: cmp w8, w9
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT: mov w9, #-32768
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -55,14 +54,13 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #24
-; CHECK-NEXT: subs w10, w8, w1, lsl #24
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: subs w8, w8, w1, lsl #24
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #24
+; CHECK-NEXT: sub w8, w0, w1
+; CHECK-NEXT: mov w9, #127
+; CHECK-NEXT: cmp w8, #127 // =127
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #128 // =128
+; CHECK-NEXT: mov w9, #-128
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -71,14 +69,13 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #28
-; CHECK-NEXT: subs w10, w8, w1, lsl #28
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: cmp w10, #0 // =0
-; CHECK-NEXT: cinv w9, w9, ge
-; CHECK-NEXT: subs w8, w8, w1, lsl #28
-; CHECK-NEXT: csel w8, w9, w8, vs
-; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: sub w8, w0, w1
+; CHECK-NEXT: mov w9, #7
+; CHECK-NEXT: cmp w8, #7 // =7
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmn w8, #8 // =8
+; CHECK-NEXT: mov w9, #-8
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index 664793bba27..c33104da2aa 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -237,30 +237,23 @@ define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
; CHECK-NEXT: ldrb w11, [x1, #1]
-; CHECK-NEXT: ldrb w12, [x0, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: ldrb w8, [x1, #2]
; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrb w8, [x0, #2]
+; CHECK-NEXT: ldrb w9, [x1, #2]
; CHECK-NEXT: mov v0.h[1], w10
-; CHECK-NEXT: ldrb w9, [x0, #3]
-; CHECK-NEXT: ldrb w10, [x1, #3]
; CHECK-NEXT: mov v1.h[1], w11
-; CHECK-NEXT: mov v0.h[2], w12
-; CHECK-NEXT: mov v1.h[2], w8
-; CHECK-NEXT: mov v0.h[3], w9
-; CHECK-NEXT: mov v1.h[3], w10
-; CHECK-NEXT: shl v1.4h, v1.4h, #8
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
-; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
-; CHECK-NEXT: mvni v2.4h, #128, lsl #8
-; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
-; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
-; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
-; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
-; CHECK-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-NEXT: ldrb w10, [x0, #3]
+; CHECK-NEXT: ldrb w11, [x1, #3]
+; CHECK-NEXT: mov v0.h[2], w8
+; CHECK-NEXT: mov v1.h[2], w9
+; CHECK-NEXT: mov v0.h[3], w10
+; CHECK-NEXT: mov v1.h[3], w11
+; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: movi v1.4h, #127
+; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: mvni v1.4h, #127
+; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret
@@ -279,21 +272,14 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ldrb w10, [x0, #1]
; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s2, w9
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: mov v2.s[1], w11
-; CHECK-NEXT: shl v2.2s, v2.2s, #24
-; CHECK-NEXT: shl v0.2s, v0.2s, #24
-; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
-; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
-; CHECK-NEXT: mvni v1.2s, #128, lsl #24
-; CHECK-NEXT: cmgt v2.2s, v2.2s, #0
-; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
-; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
-; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
-; CHECK-NEXT: ushr v0.2s, v0.2s, #24
+; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: movi v1.2s, #127
+; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mvni v1.2s, #127
+; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
@@ -337,21 +323,14 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ldrh w10, [x0, #2]
; CHECK-NEXT: ldrh w11, [x1, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fmov s2, w9
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: mov v2.s[1], w11
-; CHECK-NEXT: shl v2.2s, v2.2s, #16
-; CHECK-NEXT: shl v0.2s, v0.2s, #16
-; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
-; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
-; CHECK-NEXT: mvni v1.2s, #128, lsl #24
-; CHECK-NEXT: cmgt v2.2s, v2.2s, #0
-; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: mvn v5.8b, v4.8b
-; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
-; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
-; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
-; CHECK-NEXT: ushr v0.2s, v0.2s, #16
+; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: movi v1.2s, #127, msl #8
+; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
@@ -463,18 +442,11 @@ define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #4
-; CHECK-NEXT: shl v0.16b, v0.16b, #4
-; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
-; CHECK-NEXT: movi v2.16b, #127
-; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
-; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
-; CHECK-NEXT: mvn v5.16b, v4.16b
-; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: sshr v0.16b, v0.16b, #4
+; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.16b, #7
+; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.16b, #248
+; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z
@@ -483,18 +455,11 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
-; CHECK-NEXT: movi v2.16b, #127
-; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
-; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
-; CHECK-NEXT: mvn v5.16b, v4.16b
-; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-NEXT: sshr v0.16b, v0.16b, #7
+; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat.ll b/llvm/test/CodeGen/AArch64/uadd_sat.ll
index 61c40bc5666..f2bbc3e5de6 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat.ll
@@ -30,10 +30,10 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: func16:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #16
-; CHECK-NEXT: adds w8, w8, w1, lsl #16
-; CHECK-NEXT: csinv w8, w8, wzr, lo
-; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: cmp w8, w9
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -42,10 +42,10 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #24
-; CHECK-NEXT: adds w8, w8, w1, lsl #24
-; CHECK-NEXT: csinv w8, w8, wzr, lo
-; CHECK-NEXT: lsr w0, w8, #24
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: cmp w8, #255 // =255
+; CHECK-NEXT: mov w9, #255
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -54,10 +54,10 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #28
-; CHECK-NEXT: adds w8, w8, w1, lsl #28
-; CHECK-NEXT: csinv w8, w8, wzr, lo
-; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: cmp w8, #15 // =15
+; CHECK-NEXT: mov w9, #15
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index 55b42e79053..604207a5ff6 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -142,28 +142,25 @@ define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-LABEL: v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w11, [x1, #1]
+; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: ldrb w9, [x1, #2]
+; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: ldrb w8, [x0, #2]
-; CHECK-NEXT: mov v1.h[1], w11
-; CHECK-NEXT: ldrb w11, [x1, #3]
+; CHECK-NEXT: ldrb w9, [x1, #2]
; CHECK-NEXT: mov v0.h[1], w10
+; CHECK-NEXT: mov v1.h[1], w11
; CHECK-NEXT: ldrb w10, [x0, #3]
-; CHECK-NEXT: mov v1.h[2], w9
+; CHECK-NEXT: ldrb w11, [x1, #3]
; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: mov v1.h[3], w11
+; CHECK-NEXT: mov v1.h[2], w9
; CHECK-NEXT: mov v0.h[3], w10
-; CHECK-NEXT: shl v1.4h, v1.4h, #8
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
+; CHECK-NEXT: mov v1.h[3], w11
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ushr v0.4h, v0.4h, #8
+; CHECK-NEXT: movi d1, #0xff00ff00ff00ff
+; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret
@@ -177,20 +174,17 @@ define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w11, [x1, #1]
+; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
-; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: shl v1.2s, v1.2s, #24
-; CHECK-NEXT: shl v0.2s, v0.2s, #24
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
+; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #24
+; CHECK-NEXT: movi d1, #0x0000ff000000ff
+; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
@@ -223,20 +217,17 @@ define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-LABEL: v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrh w9, [x1]
; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: ldrh w11, [x1, #2]
+; CHECK-NEXT: ldrh w9, [x1]
; CHECK-NEXT: ldrh w10, [x0, #2]
-; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrh w11, [x1, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: shl v1.2s, v1.2s, #16
-; CHECK-NEXT: shl v0.2s, v0.2s, #16
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
+; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #16
+; CHECK-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
@@ -318,12 +309,9 @@ define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #4
-; CHECK-NEXT: shl v0.16b, v0.16b, #4
-; CHECK-NEXT: mvn v2.16b, v1.16b
-; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #4
+; CHECK-NEXT: movi v1.16b, #15
+; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z
@@ -332,12 +320,9 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: mvn v2.16b, v1.16b
-; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #7
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
diff --git a/llvm/test/CodeGen/AArch64/usub_sat.ll b/llvm/test/CodeGen/AArch64/usub_sat.ll
index 0238c263d6c..dd969bdec1a 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat.ll
@@ -30,10 +30,9 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-LABEL: func16:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #16
-; CHECK-NEXT: subs w8, w8, w1, lsl #16
-; CHECK-NEXT: csel w8, wzr, w8, lo
-; CHECK-NEXT: lsr w0, w8, #16
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csel w8, w0, w1, hi
+; CHECK-NEXT: sub w0, w8, w1
; CHECK-NEXT: ret
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -42,10 +41,9 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-LABEL: func8:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #24
-; CHECK-NEXT: subs w8, w8, w1, lsl #24
-; CHECK-NEXT: csel w8, wzr, w8, lo
-; CHECK-NEXT: lsr w0, w8, #24
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csel w8, w0, w1, hi
+; CHECK-NEXT: sub w0, w8, w1
; CHECK-NEXT: ret
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -54,10 +52,9 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-LABEL: func3:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsl w8, w0, #28
-; CHECK-NEXT: subs w8, w8, w1, lsl #28
-; CHECK-NEXT: csel w8, wzr, w8, lo
-; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csel w8, w0, w1, hi
+; CHECK-NEXT: sub w0, w8, w1
; CHECK-NEXT: ret
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index b7a8be433cc..f0cceb3621e 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -144,11 +144,8 @@ define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-NEXT: mov v1.h[2], w9
; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: mov v1.h[3], w11
-; CHECK-NEXT: shl v1.4h, v1.4h, #8
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ushr v0.4h, v0.4h, #8
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret
@@ -170,11 +167,8 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: mov v1.s[1], w11
-; CHECK-NEXT: shl v1.2s, v1.2s, #24
-; CHECK-NEXT: shl v0.2s, v0.2s, #24
; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
@@ -214,11 +208,8 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: mov v1.s[1], w11
-; CHECK-NEXT: shl v1.2s, v1.2s, #16
-; CHECK-NEXT: shl v0.2s, v0.2s, #16
; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
@@ -295,11 +286,8 @@ define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #4
-; CHECK-NEXT: shl v0.16b, v0.16b, #4
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #4
; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.usub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z
@@ -308,11 +296,8 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #7
; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
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