diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll index 78032521a85..bf186263b88 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll @@ -1,28 +1,28 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK -declare i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %a) -declare i8 @llvm.experimental.vector.reduce.and.i8.v1i8(<1 x i8> %a) -declare i16 @llvm.experimental.vector.reduce.and.i16.v1i16(<1 x i16> %a) -declare i24 @llvm.experimental.vector.reduce.and.i24.v1i24(<1 x i24> %a) -declare i32 @llvm.experimental.vector.reduce.and.i32.v1i32(<1 x i32> %a) -declare i64 @llvm.experimental.vector.reduce.and.i64.v1i64(<1 x i64> %a) -declare i128 @llvm.experimental.vector.reduce.and.i128.v1i128(<1 x i128> %a) - -declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a) -declare i8 @llvm.experimental.vector.reduce.and.i8.v9i8(<9 x i8> %a) -declare i32 @llvm.experimental.vector.reduce.and.i32.v3i32(<3 x i32> %a) -declare i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %a) -declare i24 @llvm.experimental.vector.reduce.and.i24.v4i24(<4 x i24> %a) -declare i128 @llvm.experimental.vector.reduce.and.i128.v2i128(<2 x i128> %a) -declare i32 @llvm.experimental.vector.reduce.and.i32.v16i32(<16 x i32> %a) +declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a) +declare i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a) +declare i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a) +declare i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a) +declare i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a) +declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a) +declare i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a) + +declare i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a) +declare i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a) +declare i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a) +declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a) +declare i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a) +declare i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a) +declare i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a) define i1 @test_v1i1(<1 x i1> %a) nounwind { ; CHECK-LABEL: test_v1i1: ; CHECK: // %bb.0: ; CHECK-NEXT: and w0, w0, #0x1 ; CHECK-NEXT: ret - %b = call i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %a) + %b = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a) ret i1 %b } @@ -32,7 +32,7 @@ define i8 @test_v1i8(<1 x i8> %a) nounwind { ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: umov w0, v0.b[0] ; CHECK-NEXT: ret - %b = call i8 @llvm.experimental.vector.reduce.and.i8.v1i8(<1 x i8> %a) + %b = call i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a) ret i8 %b } @@ -42,7 +42,7 @@ define i16 @test_v1i16(<1 x i16> %a) nounwind { ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: umov w0, v0.h[0] ; CHECK-NEXT: ret - %b = call i16 @llvm.experimental.vector.reduce.and.i16.v1i16(<1 x i16> %a) + %b = call i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a) ret i16 %b } @@ -50,7 +50,7 @@ define i24 @test_v1i24(<1 x i24> %a) nounwind { ; CHECK-LABEL: test_v1i24: ; CHECK: // %bb.0: ; CHECK-NEXT: ret - %b = call i24 @llvm.experimental.vector.reduce.and.i24.v1i24(<1 x i24> %a) + %b = call i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a) ret i24 %b } @@ -60,7 +60,7 @@ define i32 @test_v1i32(<1 x i32> %a) nounwind { ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret - %b = call i32 @llvm.experimental.vector.reduce.and.i32.v1i32(<1 x i32> %a) + %b = call i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a) ret i32 %b } @@ -70,7 +70,7 @@ define i64 @test_v1i64(<1 x i64> %a) nounwind { ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 ; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: ret - %b = call i64 @llvm.experimental.vector.reduce.and.i64.v1i64(<1 x i64> %a) + %b = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a) ret i64 %b } @@ -78,7 +78,7 @@ define i128 @test_v1i128(<1 x i128> %a) nounwind { ; CHECK-LABEL: test_v1i128: ; CHECK: // %bb.0: ; CHECK-NEXT: ret - %b = call i128 @llvm.experimental.vector.reduce.and.i128.v1i128(<1 x i128> %a) + %b = call i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a) ret i128 %b } @@ -89,7 +89,7 @@ define i8 @test_v3i8(<3 x i8> %a) nounwind { ; CHECK-NEXT: and w8, w8, w2 ; CHECK-NEXT: and w0, w8, #0xff ; CHECK-NEXT: ret - %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a) + %b = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a) ret i8 %b } @@ -122,7 +122,7 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind { ; CHECK-NEXT: umov w9, v0.b[7] ; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: ret - %b = call i8 @llvm.experimental.vector.reduce.and.i8.v9i8(<9 x i8> %a) + %b = call i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a) ret i8 %b } @@ -137,7 +137,7 @@ define i32 @test_v3i32(<3 x i32> %a) nounwind { ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: ret - %b = call i32 @llvm.experimental.vector.reduce.and.i32.v3i32(<3 x i32> %a) + %b = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a) ret i32 %b } @@ -154,7 +154,7 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind { ; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %b = call i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %a) + %b = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a) ret i1 %b } @@ -167,7 +167,7 @@ define i24 @test_v4i24(<4 x i24> %a) nounwind { ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: ret - %b = call i24 @llvm.experimental.vector.reduce.and.i24.v4i24(<4 x i24> %a) + %b = call i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a) ret i24 %b } @@ -177,7 +177,7 @@ define i128 @test_v2i128(<2 x i128> %a) nounwind { ; CHECK-NEXT: and x0, x0, x2 ; CHECK-NEXT: and x1, x1, x3 ; CHECK-NEXT: ret - %b = call i128 @llvm.experimental.vector.reduce.and.i128.v2i128(<2 x i128> %a) + %b = call i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a) ret i128 %b } @@ -193,6 +193,6 @@ define i32 @test_v16i32(<16 x i32> %a) nounwind { ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: ret - %b = call i32 @llvm.experimental.vector.reduce.and.i32.v16i32(<16 x i32> %a) + %b = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a) ret i32 %b } |
