diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll index 31cc59c10b9..2983e240977 100644 --- a/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll +++ b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st -verify-machineinstrs < %s | FileCheck %s ; Test cases are generated from: ; long long NAME(PARAM a, PARAM b) { @@ -24,7 +24,7 @@ define i64 @ll_a_op_b__2(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB0_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -52,7 +52,7 @@ define i64 @ll_a_op_b__1(i64 %a, i64 %b) { ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB1_2: // %if.end ; CHECK-NEXT: cmn x8, #1 // =1 -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -80,7 +80,7 @@ define i64 @ll_a_op_b_0(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB2_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -108,7 +108,7 @@ define i64 @ll_a_op_b_1(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB3_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -136,7 +136,7 @@ define i64 @ll_a_op_b_2(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB4_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -163,7 +163,7 @@ define i64 @ll_a__2(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB5_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -189,7 +189,7 @@ define i64 @ll_a__1(i64 %a, i64 %b) { ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB6_2: // %if.end ; CHECK-NEXT: cmn x0, #1 // =1 -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -215,7 +215,7 @@ define i64 @ll_a_0(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB7_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -241,7 +241,7 @@ define i64 @ll_a_1(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB8_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: @@ -267,7 +267,7 @@ define i64 @ll_a_2(i64 %a, i64 %b) { ; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB9_2: // %if.end -; CHECK-NEXT: csinc x8, x1, xzr, eq +; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: ret entry: |
