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-rw-r--r--llvm/test/CodeGen/AArch64/uadd_sat_vec.ll83
1 files changed, 36 insertions, 47 deletions
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index 55b42e79053..4ff14c72e1f 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -142,28 +142,25 @@ define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
; CHECK-LABEL: v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w11, [x1, #1]
+; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: ldrb w9, [x1, #2]
+; CHECK-NEXT: ldrb w11, [x1, #1]
+; CHECK-NEXT: ldrb w12, [x0, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: ldrb w8, [x0, #2]
-; CHECK-NEXT: mov v1.h[1], w11
-; CHECK-NEXT: ldrb w11, [x1, #3]
+; CHECK-NEXT: ldrb w8, [x1, #2]
+; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.h[1], w10
-; CHECK-NEXT: ldrb w10, [x0, #3]
-; CHECK-NEXT: mov v1.h[2], w9
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: mov v1.h[3], w11
-; CHECK-NEXT: mov v0.h[3], w10
-; CHECK-NEXT: shl v1.4h, v1.4h, #8
-; CHECK-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
+; CHECK-NEXT: ldrb w9, [x0, #3]
+; CHECK-NEXT: ldrb w10, [x1, #3]
+; CHECK-NEXT: mov v1.h[1], w11
+; CHECK-NEXT: mov v0.h[2], w12
+; CHECK-NEXT: mov v1.h[2], w8
+; CHECK-NEXT: mov v0.h[3], w9
+; CHECK-NEXT: mov v1.h[3], w10
+; CHECK-NEXT: movi d2, #0xff00ff00ff00ff
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ushr v0.4h, v0.4h, #8
+; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret
@@ -177,20 +174,17 @@ define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w11, [x1, #1]
+; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1]
-; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: shl v1.2s, v1.2s, #24
-; CHECK-NEXT: shl v0.2s, v0.2s, #24
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
-; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #24
+; CHECK-NEXT: mov v2.s[1], w11
+; CHECK-NEXT: movi d1, #0x0000ff000000ff
+; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
+; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
@@ -223,20 +217,17 @@ define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-LABEL: v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrh w9, [x1]
; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: ldrh w11, [x1, #2]
+; CHECK-NEXT: ldrh w9, [x1]
; CHECK-NEXT: ldrh w10, [x0, #2]
-; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: ldrh w11, [x1, #2]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v1.s[1], w11
+; CHECK-NEXT: fmov s2, w9
; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: shl v1.2s, v1.2s, #16
-; CHECK-NEXT: shl v0.2s, v0.2s, #16
-; CHECK-NEXT: mvn v2.8b, v1.8b
-; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
-; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #16
+; CHECK-NEXT: mov v2.s[1], w11
+; CHECK-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
+; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
@@ -318,12 +309,11 @@ define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #4
-; CHECK-NEXT: shl v0.16b, v0.16b, #4
-; CHECK-NEXT: mvn v2.16b, v1.16b
-; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: movi v2.16b, #15
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #4
+; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z
@@ -332,12 +322,11 @@ define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: shl v0.16b, v0.16b, #7
-; CHECK-NEXT: mvn v2.16b, v1.16b
-; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: movi v2.16b, #1
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: ushr v0.16b, v0.16b, #7
+; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z
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