diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll | 64 |
1 files changed, 35 insertions, 29 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll index 7252bb1c804..bb2b450d173 100644 --- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll +++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll @@ -395,40 +395,45 @@ define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 { define <8 x i8> @fptosi_i8(<8 x half> %a) #0 { ; CHECK-LABEL: fptosi_i8: -; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h -; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h -; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] -; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] -; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] -; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]] -; CHECK-NEXT: xtn v0.8b, [[I16]].8h -; CHECK-NEXT: ret +; CHECK-FP16-NEXT: fcvtzs [[LO:v[0-9]+\.8h]], v0.8h +; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h +; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h +; CHECK-CVT-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] +; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] +; CHECK-CVT-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] +; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] +; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h +; CHECK-FP16-NEXT: xtn v0.8b, [[LO]] +; CHECK-NEXT: ret %1 = fptosi<8 x half> %a to <8 x i8> ret <8 x i8> %1 } define <8 x i16> @fptosi_i16(<8 x half> %a) #0 { ; CHECK-LABEL: fptosi_i16: -; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h -; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h -; CHECK-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] -; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] -; CHECK-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] -; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]] -; CHECK-NEXT: ret +; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h +; CHECK-CVT_DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h +; CHECK-CVT_DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h +; CHECK-CVT_DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] +; CHECK-CVT_DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] +; CHECK-CVT_DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] +; CHECK-CVT_DAG: xtn2 [[I16]].8h, [[HIF32]] +; CHECK-COMMON_NEXT: ret %1 = fptosi<8 x half> %a to <8 x i16> ret <8 x i16> %1 } define <8 x i8> @fptoui_i8(<8 x half> %a) #0 { ; CHECK-LABEL: fptoui_i8: -; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h -; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h -; CHECK-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] -; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] -; CHECK-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] -; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]] -; CHECK-NEXT: xtn v0.8b, [[I16]].8h +; CHECK-FP16-NEXT: fcvtzu [[LO:v[0-9]+\.8h]], v0.8h +; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h +; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h +; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] +; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] +; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] +; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] +; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h +; CHECK-FP16-NEXT: xtn v0.8b, [[LO]] ; CHECK-NEXT: ret %1 = fptoui<8 x half> %a to <8 x i8> ret <8 x i8> %1 @@ -436,13 +441,14 @@ define <8 x i8> @fptoui_i8(<8 x half> %a) #0 { define <8 x i16> @fptoui_i16(<8 x half> %a) #0 { ; CHECK-LABEL: fptoui_i16: -; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h -; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h -; CHECK-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] -; CHECK-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] -; CHECK-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] -; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]] -; CHECK-NEXT: ret +; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h +; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h +; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h +; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] +; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] +; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] +; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] +; CHECK-NEXT: ret %1 = fptoui<8 x half> %a to <8 x i16> ret <8 x i16> %1 } |
