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-rw-r--r--llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
index b2bfc13967a..8c81cf43e68 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -4,7 +4,7 @@
; Test for bug in misched memory dependency calculation.
;
; CHECK: ********** MI Scheduling **********
-; CHECK: misched_bug:BB#0 entry
+; CHECK: misched_bug:%bb.0 entry
; CHECK: SU(2): %2<def> = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
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