diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir | 74 |
1 files changed, 49 insertions, 25 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir index b78c7a55e79..008c43fad63 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir @@ -1,11 +1,17 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# WARNING: update_mir_test_checks.py does not include the constant pools output, +# so this test requires manual fixing up after running the script. + # RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s --- | - ; ModuleID = 'shufflevec-only-legal.ll' - source_filename = "shufflevec-only-legal.ll" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64" + define <2 x float> @shuffle_v2f32(<2 x float> %a, <2 x float> %b) { + %shuf = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 0> + ret <2 x float> %shuf + } + define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) { %shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0> ret <4 x i32> %shuf @@ -23,19 +29,52 @@ ... --- +name: shuffle_v2f32 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + liveins: $d0, $d1 + + ; CHECK-LABEL: name: shuffle_v2f32 + ; CHECK: constants: + ; CHECK: - id: 0 + ; CHECK: value: '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>' + ; CHECK: alignment: 8 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 + ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub + ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub + ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 + ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[LDRDui]], %subreg.dsub + ; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG2]] + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub + ; CHECK: $d0 = COPY [[COPY2]] + ; CHECK: RET_ReallyLR implicit $d0 + %0:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s32>) = COPY $d1 + %4:gpr(s32) = G_CONSTANT i32 1 + %5:gpr(s32) = G_CONSTANT i32 0 + %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32) + %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, %3(<2 x s32>) + $d0 = COPY %2(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- name: shuffle_v4i32 alignment: 2 legalized: true regBankSelected: true tracksRegLiveness: true -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - - { id: 3, class: fpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - - { id: 6, class: gpr } body: | bb.1 (%ir-block.0): liveins: $q0, $q1 @@ -71,15 +110,6 @@ alignment: 2 legalized: true regBankSelected: true tracksRegLiveness: true -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - - { id: 3, class: fpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - - { id: 6, class: gpr } - - { id: 7, class: gpr } body: | bb.1 (%ir-block.0): liveins: $q0, $q1 @@ -116,12 +146,6 @@ alignment: 2 legalized: true regBankSelected: true tracksRegLiveness: true -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - - { id: 3, class: fpr } - - { id: 4, class: gpr } body: | bb.1 (%ir-block.0): liveins: $q0, $q1 |
