diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def | 23 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 47 |
2 files changed, 58 insertions, 12 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def index de85b383b63..9655db82380 100644 --- a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -65,6 +65,11 @@ RegisterBankInfo::PartialMapping PartMappings[] { {0, 512, FPRRegBank} }; +enum ValueMappingIdx { + First3OpsIdx = 7, + Last3OpsIdx = 25 +}; + // ValueMappings. RegisterBankInfo::ValueMapping ValMappings[] { /* BreakDown, NumBreakDowns */ @@ -81,7 +86,23 @@ RegisterBankInfo::ValueMapping ValMappings[] { // 5: FPR 256-bit value. {&PartMappings[5], 1}, // 6: FPR 512-bit value. - {&PartMappings[6], 1} + {&PartMappings[6], 1}, + // 3-operands instructions (all binary operations should end up with one of + // those mapping). + // 7: GPR 32-bit value. <-- This must match First3OpsIdx. + {&PartMappings[0], 1}, {&PartMappings[0], 1}, {&PartMappings[0], 1}, + // 10: GPR 64-bit value. + {&PartMappings[1], 1}, {&PartMappings[1], 1}, {&PartMappings[1], 1}, + // 13: FPR 32-bit value. + {&PartMappings[2], 1}, {&PartMappings[2], 1}, {&PartMappings[2], 1}, + // 16: FPR 64-bit value. + {&PartMappings[3], 1}, {&PartMappings[3], 1}, {&PartMappings[3], 1}, + // 19: FPR 128-bit value. + {&PartMappings[4], 1}, {&PartMappings[4], 1}, {&PartMappings[4], 1}, + // 22: FPR 256-bit value. + {&PartMappings[5], 1}, {&PartMappings[5], 1}, {&PartMappings[5], 1}, + // 25: FPR 512-bit value. <-- This must match Last3OpsIdx. + {&PartMappings[6], 1}, {&PartMappings[6], 1}, {&PartMappings[6], 1} }; } // End AArch64 namespace. diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 3350dab08d8..9feeba174d7 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -130,21 +130,46 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) CHECK_PARTIALMAP(FPR512, 0, 512, RBFPR); // Check value mapping. -#define CHECK_VALUEMAP(Idx) \ +#define CHECK_VALUEMAP_IMPL(ValIdx, PartIdx) \ do { \ - const ValueMapping &Map = AArch64::ValMappings[Idx]; \ + unsigned PartialMapBaseIdx = AArch64::PartialMappingIdx::PartIdx; \ + (void) PartialMapBaseIdx; \ + const ValueMapping &Map = AArch64::ValMappings[ValIdx]; \ (void) Map; \ - assert(Map.BreakDown == &AArch64::PartMappings[Idx] && \ - Map.NumBreakDowns == 1 && #Idx " is incorrectly initialized"); \ + assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \ + Map.NumBreakDowns == 1 && #ValIdx " " #PartIdx \ + " is incorrectly initialized"); \ + } while (0) + +#define CHECK_VALUEMAP(Idx) \ + CHECK_VALUEMAP_IMPL(AArch64::PartialMappingIdx::Idx, Idx) + + CHECK_VALUEMAP(GPR32); + CHECK_VALUEMAP(GPR64); + CHECK_VALUEMAP(FPR32); + CHECK_VALUEMAP(FPR64); + CHECK_VALUEMAP(FPR128); + CHECK_VALUEMAP(FPR256); + CHECK_VALUEMAP(FPR512); + +// Check the value mapping for 3-operands instructions where all the operands +// map to the same value mapping. +#define CHECK_VALUEMAP_3OPS(Idx) \ + do { \ + unsigned BaseIdx = \ + AArch64::First3OpsIdx + AArch64::PartialMappingIdx::Idx * 3; \ + CHECK_VALUEMAP_IMPL(BaseIdx, Idx); \ + CHECK_VALUEMAP_IMPL(BaseIdx + 1, Idx); \ + CHECK_VALUEMAP_IMPL(BaseIdx + 2, Idx); \ } while (0) - CHECK_VALUEMAP(AArch64::PartialMappingIdx::GPR32); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::GPR64); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::FPR32); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::FPR64); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::FPR128); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::FPR256); - CHECK_VALUEMAP(AArch64::PartialMappingIdx::FPR512); + CHECK_VALUEMAP_3OPS(GPR32); + CHECK_VALUEMAP_3OPS(GPR64); + CHECK_VALUEMAP_3OPS(FPR32); + CHECK_VALUEMAP_3OPS(FPR64); + CHECK_VALUEMAP_3OPS(FPR128); + CHECK_VALUEMAP_3OPS(FPR256); + CHECK_VALUEMAP_3OPS(FPR512); assert(verify(TRI) && "Invalid register bank information"); } |
