diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Support/TargetParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Support/Triple.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 5 |
5 files changed, 29 insertions, 4 deletions
diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp index a1d4aaa1890..42fab671a25 100644 --- a/llvm/lib/Support/TargetParser.cpp +++ b/llvm/lib/Support/TargetParser.cpp @@ -578,6 +578,7 @@ static StringRef getArchSynonym(StringRef Arch) { .Cases("v8", "v8a", "aarch64", "arm64", "v8-a") .Case("v8.1a", "v8.1-a") .Case("v8.2a", "v8.2-a") + .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") .Default(Arch); @@ -721,6 +722,7 @@ unsigned llvm::ARM::parseArchProfile(StringRef Arch) { case ARM::AK_ARMV8MBaseline: return ARM::PK_M; case ARM::AK_ARMV7R: + case ARM::AK_ARMV8R: return ARM::PK_R; case ARM::AK_ARMV7A: case ARM::AK_ARMV7K: @@ -768,6 +770,7 @@ unsigned llvm::ARM::parseArchVersion(StringRef Arch) { case ARM::AK_ARMV8A: case ARM::AK_ARMV8_1A: case ARM::AK_ARMV8_2A: + case ARM::AK_ARMV8R: case ARM::AK_ARMV8MBaseline: case ARM::AK_ARMV8MMainline: return 8; diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp index 1470563a6e9..19d278d4578 100644 --- a/llvm/lib/Support/Triple.cpp +++ b/llvm/lib/Support/Triple.cpp @@ -550,6 +550,8 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) { return Triple::ARMSubArch_v8_1a; case ARM::AK_ARMV8_2A: return Triple::ARMSubArch_v8_2a; + case ARM::AK_ARMV8R: + return Triple::ARMSubArch_v8r; case ARM::AK_ARMV8MBaseline: return Triple::ARMSubArch_v8m_baseline; case ARM::AK_ARMV8MMainline: diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 1aa975bd54a..240306e7159 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -353,6 +353,8 @@ def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", []>; def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", "Cortex-R7 ARM processors", []>; +def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", + "Cortex-R52 ARM processors", []>; def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; @@ -474,6 +476,19 @@ def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, FeatureCRC, FeatureRAS]>; +def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, + FeatureRClass, + FeatureDB, + FeatureHWDiv, + FeatureHWDivARM, + FeatureT2XtPk, + FeatureDSP, + FeatureCRC, + FeatureMP, + FeatureVirtualization, + FeatureFPARMv8, + FeatureNEON]>; + def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", [HasV8MBaselineOps, FeatureNoARM, @@ -804,6 +819,8 @@ def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, FeatureCrypto, FeatureCRC]>; +def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 5788ce6c007..4facb7fcbdd 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -605,9 +605,11 @@ static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU, if (CPU == "xscale") return ARMBuildAttrs::v5TEJ; - if (Subtarget->hasV8Ops()) + if (Subtarget->hasV8Ops()) { + if (Subtarget->isRClass()) + return ARMBuildAttrs::v8_R; return ARMBuildAttrs::v8_A; - else if (Subtarget->hasV8MMainlineOps()) + } else if (Subtarget->hasV8MMainlineOps()) return ARMBuildAttrs::v8_M_Main; else if (Subtarget->hasV7Ops()) { if (Subtarget->isMClass() && Subtarget->hasDSP()) diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 6d528b8d62f..6c056547eee 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -43,7 +43,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, - CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3, + CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3, CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73, Krait, Swift, ExynosM1 }; @@ -53,7 +53,8 @@ protected: enum ARMArchEnum { ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r, - ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline + ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline, + ARMv8r }; public: |
