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-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td2
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td2
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 7de6791f2e4..84c9203c378 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -18,7 +18,7 @@ def HaswellModel : SchedMachineModel {
let IssueWidth = 4;
let MinLatency = 0; // 0 = Out-of-order execution.
let LoadLatency = 4;
- let ILPWindow = 40;
+ let ILPWindow = 30;
let MispredictPenalty = 16;
}
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 74d5f1b6eba..b36b3ad947e 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -19,7 +19,7 @@ def SandyBridgeModel : SchedMachineModel {
let IssueWidth = 4;
let MinLatency = 0; // 0 = Out-of-order execution.
let LoadLatency = 4;
- let ILPWindow = 30;
+ let ILPWindow = 20;
let MispredictPenalty = 16;
}
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