diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2256fe02696..42c5339f11f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -19051,23 +19051,21 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, if (Opc == X86ISD::PCMPGT && !Subtarget.hasSSE42()) { assert(Subtarget.hasSSE2() && "Don't know how to lower!"); - // First cast everything to the right type. - Op0 = DAG.getBitcast(MVT::v4i32, Op0); - Op1 = DAG.getBitcast(MVT::v4i32, Op1); - // Since SSE has no unsigned integer comparisons, we need to flip the sign // bits of the inputs before performing those operations. The lower // compare is always unsigned. SDValue SB; if (FlipSigns) { - SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32); + SB = DAG.getConstant(0x8000000080000000ULL, dl, MVT::v2i64); } else { - SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32); - SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32); - SB = DAG.getBuildVector(MVT::v4i32, dl, {Sign, Zero, Sign, Zero}); + SB = DAG.getConstant(0x0000000080000000ULL, dl, MVT::v2i64); } - Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); - Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); + Op0 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op0, SB); + Op1 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op1, SB); + + // Cast everything to the right type. + Op0 = DAG.getBitcast(MVT::v4i32, Op0); + Op1 = DAG.getBitcast(MVT::v4i32, Op1); // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); |
