diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedPredicates.td | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86SchedPredicates.td b/llvm/lib/Target/X86/X86SchedPredicates.td index 27aaeb19358..abb86119d45 100644 --- a/llvm/lib/Target/X86/X86SchedPredicates.td +++ b/llvm/lib/Target/X86/X86SchedPredicates.td @@ -19,11 +19,9 @@ // different zero-idioms. def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>; -// A predicate used to check if an instruction is a LEA, and if it uses all -// three source operands: base, index, and offset. +// A predicate used to check if a LEA instruction uses all three source +// operands: base, index, and offset. def IsThreeOperandsLEAPredicate: CheckAll<[ - CheckOpcode<[LEA32r, LEA64r, LEA64_32r, LEA16r]>, - // isRegOperand(Base) CheckIsRegOperand<1>, CheckNot<CheckInvalidRegOperand<1>>, @@ -42,8 +40,17 @@ def IsThreeOperandsLEAPredicate: CheckAll<[ ]> ]>; +def LEACases : MCOpcodeSwitchCase< + [LEA32r, LEA64r, LEA64_32r, LEA16r], + MCReturnStatement<IsThreeOperandsLEAPredicate> +>; + +// Used to generate the body of a TII member function. +def IsThreeOperandsLEABody : + MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>; + // This predicate evaluates to true only if the input machine instruction is a // 3-operands LEA. Tablegen automatically generates a new method for it in // X86GenInstrInfo. def IsThreeOperandsLEAFn : - TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEAPredicate>; + TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEABody>; |
