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-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td46
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td27
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td52
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td22
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td26
5 files changed, 14 insertions, 159 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 45d055ec4ea..2308ba50297 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -314,8 +314,8 @@ def : WriteRes<WriteNop, []>;
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
-defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
+defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3>;
+defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3>;
// Remaining instrs.
@@ -681,19 +681,6 @@ def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
"VPSRAVD(Y?)rr",
"VPSRLVD(Y?)rr")>;
-def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
- "(V?)PHADDD(Y?)rr",
- "(V?)PHADDSW(Y?)rr",
- "(V?)PHADDW(Y?)rr",
- "(V?)PHSUBD(Y?)rr",
- "(V?)PHSUBSW(Y?)rr",
- "(V?)PHSUBW(Y?)rr")>;
-
def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
@@ -876,11 +863,7 @@ def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
- "(V?)HADDPD(Y?)rr",
- "(V?)HADDPS(Y?)rr",
- "(V?)HSUBPD(Y?)rr",
- "(V?)HSUBPS(Y?)rr")>;
+def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
let Latency = 5;
@@ -1509,19 +1492,6 @@ def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
"VPSRAVDrm",
"VPSRLVDrm")>;
-def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
- let Latency = 8;
- let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
-}
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rm",
- "(V?)PHADDDrm",
- "(V?)PHADDSWrm",
- "(V?)PHADDWrm",
- "(V?)PHSUBDrm",
- "(V?)PHSUBSWrm",
- "(V?)PHSUBWrm")>;
-
def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
@@ -1760,16 +1730,6 @@ def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
}
def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
-def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
- let Latency = 10;
- let NumMicroOps = 4;
- let ResourceCycles = [1,2,1];
-}
-def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
- "(V?)HADDPSrm",
- "(V?)HSUBPDrm",
- "(V?)HSUBPSrm")>;
-
def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
let Latency = 10;
let NumMicroOps = 4;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 4b4c14a3c75..f5c635cd2a2 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -556,8 +556,8 @@ def : InstRW<[HWWriteFXTRACT], (instregex "FXTRACT")>;
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1, 2], 3>;
-defm : HWWriteResPair<WritePHAdd, [HWPort1, HWPort5], 3, [1, 2], 3>;
+defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>;
+defm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 6>;
//=== Floating Point XMM and YMM Instructions ===//
@@ -1574,19 +1574,6 @@ def: InstRW<[HWWriteResGroup55], (instregex "VPSLLVD(Y?)rr",
"VPSRAVD(Y?)rr",
"VPSRLVD(Y?)rr")>;
-def HWWriteResGroup56 : SchedWriteRes<[HWPort5,HWPort15]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
- "(V?)PHADDD(Y?)rr",
- "(V?)PHADDSW(Y?)rr",
- "(V?)PHADDW(Y?)rr",
- "(V?)PHSUBD(Y?)rr",
- "(V?)PHSUBSW(Y?)rr",
- "(V?)PHSUBW(Y?)rr")>;
-
def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
@@ -2081,16 +2068,6 @@ def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
}
def: InstRW<[HWWriteResGroup95], (instrs IMUL32r, MUL32r, MULX32rr)>;
-def HWWriteResGroup96 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
- let Latency = 11;
- let NumMicroOps = 4;
- let ResourceCycles = [1,2,1];
-}
-def: InstRW<[HWWriteResGroup96], (instregex "(V?)HADDPDrm",
- "(V?)HADDPSrm",
- "(V?)HSUBPDrm",
- "(V?)HSUBPSrm")>;
-
def HWWriteResGroup96_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let Latency = 12;
let NumMicroOps = 4;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index f0fc9a7f42f..38990797795 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -177,10 +177,12 @@ defm : SBWriteResPair<WritePSADBW, [SBPort0], 5>;
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : SBWriteResPair<WriteFHAdd, [SBPort1], 3>;
-defm : SBWriteResPair<WritePHAdd, [SBPort15], 1>;
+defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>;
+defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 6>;
+////////////////////////////////////////////////////////////////////////////////
// String instructions.
+////////////////////////////////////////////////////////////////////////////////
// Packed Compare Implicit Length Strings, Return Mask
def : WriteRes<WritePCmpIStrM, [SBPort0]> {
@@ -618,19 +620,6 @@ def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL",
"SHL(8|16|32|64)rCL",
"SHR(8|16|32|64)rCL")>;
-def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
- "(V?)PHADDDrr",
- "(V?)PHADDSWrr",
- "(V?)PHADDWrr",
- "(V?)PHSUBDrr",
- "(V?)PHSUBSWrr",
- "(V?)PHSUBWrr")>;
-
def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
let Latency = 2;
let NumMicroOps = 3;
@@ -784,11 +773,7 @@ def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
}
def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI642SSrr",
- "(V?)CVTSI2SSrr",
- "(V?)HADDPD(Y?)rr",
- "(V?)HADDPS(Y?)rr",
- "(V?)HSUBPD(Y?)rr",
- "(V?)HSUBPS(Y?)rr")>;
+ "(V?)CVTSI2SSrr")>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5;
@@ -1453,18 +1438,6 @@ def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m",
"LD_F64m",
"LD_F80m")>;
-def SBWriteResGroup96 : SchedWriteRes<[SBPort23,SBPort15]> {
- let Latency = 9;
- let NumMicroOps = 4;
- let ResourceCycles = [1,3];
-}
-def: InstRW<[SBWriteResGroup96], (instregex "(V?)PHADDDrm",
- "(V?)PHADDSWrm",
- "(V?)PHADDWrm",
- "(V?)PHSUBDrm",
- "(V?)PHSUBSWrm",
- "(V?)PHSUBWrm")>;
-
def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 9;
let NumMicroOps = 4;
@@ -1618,16 +1591,6 @@ def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm",
"VCVTPD2PSYrm",
"VCVTTPD2DQYrm")>;
-def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
- let Latency = 11;
- let NumMicroOps = 4;
- let ResourceCycles = [1,2,1];
-}
-def: InstRW<[SBWriteResGroup109], (instregex "(V?)HADDPDrm",
- "(V?)HADDPSrm",
- "(V?)HSUBPDrm",
- "(V?)HSUBPSrm")>;
-
def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 12;
let NumMicroOps = 2;
@@ -1650,10 +1613,7 @@ def SBWriteResGroup113 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SBWriteResGroup113], (instregex "VHADDPDYrm",
- "VHADDPSYrm",
- "VHSUBPDYrm",
- "VHSUBPSYrm")>;
+def: InstRW<[SBWriteResGroup113], (instregex "VH(ADD|SUB)(PD|PS)Yrm")>;
def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 13;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 9b1603bc823..7024e1dd52e 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -320,7 +320,7 @@ def : WriteRes<WriteNop, []>;
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : SKLWriteResPair<WriteFHAdd, [SKLPort1], 3>;
+defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
defm : SKLWriteResPair<WritePHAdd, [SKLPort15], 1>;
// Remaining instrs.
@@ -1236,16 +1236,6 @@ def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
-def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
- let Latency = 6;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SKLWriteResGroup77], (instregex "(V?)HADDPD(Y?)rr",
- "(V?)HADDPS(Y?)rr",
- "(V?)HSUBPD(Y?)rr",
- "(V?)HSUBPS(Y?)rr")>;
-
def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 3;
@@ -2163,16 +2153,6 @@ def SKLWriteResGroup158 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
}
def: InstRW<[SKLWriteResGroup158], (instregex "VSQRTPSYr")>;
-def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
- let Latency = 12;
- let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
-}
-def: InstRW<[SKLWriteResGroup159], (instregex "(V?)HADDPDrm",
- "(V?)HADDPSrm",
- "(V?)HSUBPDrm",
- "(V?)HSUBPSrm")>;
-
def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 12;
let NumMicroOps = 4;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index b3b30e460ed..da59964d4b6 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -320,7 +320,7 @@ def : WriteRes<WriteNop, []>;
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : SKXWriteResPair<WriteFHAdd, [SKXPort1], 3>;
+defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
defm : SKXWriteResPair<WritePHAdd, [SKXPort15], 1>;
// Remaining instrs.
@@ -2415,21 +2415,9 @@ def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let ResourceCycles = [2,1];
}
def: InstRW<[SKXWriteResGroup82], (instregex "CVTSI642SSrr",
- "HADDPDrr",
- "HADDPSrr",
- "HSUBPDrr",
- "HSUBPSrr",
"VCVTSI642SSrr",
"VCVTSI642SSZrr",
- "VCVTUSI642SSZrr",
- "VHADDPDYrr",
- "VHADDPDrr",
- "VHADDPSYrr",
- "VHADDPSrr",
- "VHSUBPDYrr",
- "VHSUBPDrr",
- "VHSUBPSYrr",
- "VHSUBPSrr")>;
+ "VCVTUSI642SSZrr")>;
def SKXWriteResGroup83 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
let Latency = 6;
@@ -4538,16 +4526,6 @@ def: InstRW<[SKXWriteResGroup177], (instregex "VCVTPS2QQZrm(b?)",
"VCVTTPS2QQZrm(b?)",
"VCVTTPS2UQQZrm(b?)")>;
-def SKXWriteResGroup178 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
- let Latency = 12;
- let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
-}
-def: InstRW<[SKXWriteResGroup178], (instregex "(V?)HADDPDrm",
- "(V?)HADDPSrm",
- "(V?)HSUBPDrm",
- "(V?)HSUBPSrm")>;
-
def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 12;
let NumMicroOps = 4;
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