diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleGeneric.td | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index dd86ba767b1..425773dc57f 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1774,6 +1774,19 @@ let AddedComplexity = 41 in { def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6; } +let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in { + class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> : + PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>, + PseudoInstExpansion<(JumpInst Opnd:$target)>; +} + +def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6; + +def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), + (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)), + (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6; + def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6; def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6; diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index 10393280cf0..e8a0a30b8e9 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -384,7 +384,7 @@ def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6, BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6, BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6, BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, - BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, + BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6, ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6, B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>; |
