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-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index de3b51ca5c7..f20ee1b91ac 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8940,7 +8940,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
inITBlock())
return Match_RequiresNotITBlock;
// LSL with zero immediate is not allowed in an IT block
- if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock())
+ if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
return Match_RequiresNotITBlock;
} else if (isThumbOne()) {
// Some high-register supporting Thumb1 encodings only allow both registers
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