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-rw-r--r--llvm/lib/Target/ARM64/ARM64.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64.td b/llvm/lib/Target/ARM64/ARM64.td
index 653f1574158..c473205f17c 100644
--- a/llvm/lib/Target/ARM64/ARM64.td
+++ b/llvm/lib/Target/ARM64/ARM64.td
@@ -34,7 +34,7 @@ def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
/// Cyclone has register move instructions which are "free".
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
- "Has zereo-cycle register moves">;
+ "Has zero-cycle register moves">;
/// Cyclone has instructions which zero registers for "free".
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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