summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/MipsLegalizerInfo.cpp8
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp2
2 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index f820da3dbc7..087a41cca6e 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -188,10 +188,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({s32, s64});
- getActionDefinitionsBuilder({G_FABS, G_FSQRT})
+ getActionDefinitionsBuilder(G_FSQRT)
.legalFor({s32, s64});
- getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+ getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
.legalIf([=, &ST](const LegalityQuery &Query) {
if (CheckTyN(0, Query, {s32, s64}))
return true;
@@ -425,6 +425,10 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
case Intrinsic::mips_fdiv_w:
case Intrinsic::mips_fdiv_d:
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST);
+ case Intrinsic::mips_fmax_a_w:
+ return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
+ case Intrinsic::mips_fmax_a_d:
+ return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
default:
break;
}
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 8af360a33e3..ab4be5fa102 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -539,7 +539,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
&Mips::ValueMappings[Mips::GPRIdx]});
MappingID = CustomMappingID;
break;
- case G_FABS:
case G_FSQRT:
OperandsMapping = getFprbMapping(Op0Size);
break;
@@ -547,6 +546,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_FSUB:
case G_FMUL:
case G_FDIV:
+ case G_FABS:
OperandsMapping = getFprbMapping(Op0Size);
if (Op0Size == 128)
OperandsMapping = getMSAMapping(MF);
OpenPOWER on IntegriCloud