diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 23 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 28 |
2 files changed, 3 insertions, 48 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 23d88e55dc4..0b7a3cbaa9f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -861,28 +861,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, switch (CCCode) { default: llvm_unreachable("Unknown integer comparison!"); case ISD::SETEQ: - case ISD::SETNE: { - SDValue OpL, OpR; - - OpL = GetPromotedInteger(NewLHS); - OpR = GetPromotedInteger(NewRHS); - - // We would prefer to promote the comparison operand with sign extension, - // if we find the operand is actually to truncate an AssertSext. With this - // optimization, we can avoid inserting real truncate instruction, which - // is redudant eventually. - if (OpL->getOpcode() == ISD::AssertSext && - cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() && - OpR->getOpcode() == ISD::AssertSext && - cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) { - NewLHS = OpL; - NewRHS = OpR; - } else { - NewLHS = ZExtPromotedInteger(NewLHS); - NewRHS = ZExtPromotedInteger(NewRHS); - } - break; - } + case ISD::SETNE: case ISD::SETUGE: case ISD::SETUGT: case ISD::SETULE: diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 1ca496bc3cf..e264cd9ae4a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -757,28 +757,6 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); } -static ISD::NodeType getPreferredExtendForValue(const Value *V) { - // For the users of the source value being used for compare instruction, if - // the number of signed predicate is greater than unsigned predicate, we - // prefer to use SIGN_EXTEND. - // - // With this optimization, we would be able to reduce some redundant sign or - // zero extension instruction, and eventually more machine CSE opportunities - // can be exposed. - ISD::NodeType ExtendKind = ISD::ANY_EXTEND; - unsigned int NumOfSigned = 0, NumOfUnsigned = 0; - for (const User *U : V->users()) { - if (const CmpInst *CI = dyn_cast<CmpInst>(U)) { - NumOfSigned += CI->isSigned(); - NumOfUnsigned += CI->isUnsigned(); - } - } - if (NumOfSigned > NumOfUnsigned) - ExtendKind = ISD::SIGN_EXTEND; - - return ExtendKind; -} - /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. @@ -787,7 +765,6 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, SDValue *Flag, const Value *V) const { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - ISD::NodeType ExtendKind = getPreferredExtendForValue(V); // Get the list of the values's legal parts. unsigned NumRegs = Regs.size(); @@ -796,9 +773,8 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, EVT ValueVT = ValueVTs[Value]; unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); MVT RegisterVT = RegVTs[Value]; - - if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) - ExtendKind = ISD::ZERO_EXTEND; + ISD::NodeType ExtendKind = + TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], NumParts, RegisterVT, V, ExtendKind); |
