diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMachineFunction.cpp | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index c5a259b8ccf..f80efb18507 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1044,7 +1044,7 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianess. +/// according to the given endianness. static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) { @@ -1064,7 +1064,7 @@ static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, } /// Read four bytes from the ArrayRef and return 32 bit word sorted -/// according to the given endianess +/// according to the given endianness. static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) { diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index b30fc4a0119..179695bc698 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -500,7 +500,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned RegOp = OpNum; if (!Subtarget->isGP64bit()){ - // Endianess reverses which register holds the high or low value + // Endianness reverses which register holds the high or low value // between M and L. switch(ExtraCode[0]) { case 'M': diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index e92d3aef72e..d0609b15341 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -68,7 +68,7 @@ void MipsFunctionInfo::createEhDataRegsFI() { void MipsFunctionInfo::createISRRegFI() { // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. // The current implementation only supports Mips32r2+ not Mips64rX. Status - // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture, + // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, // however Mips32r2+ is the supported architecture. const TargetRegisterClass *RC = &Mips::GPR32RegClass; |
