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-rw-r--r--llvm/lib/Analysis/TargetTransformInfo.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp10
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp8
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h1
4 files changed, 16 insertions, 7 deletions
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index ed7005e5e52..bd957898834 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -219,6 +219,10 @@ unsigned TargetTransformInfo::getCacheLineSize() const {
return TTIImpl->getCacheLineSize();
}
+unsigned TargetTransformInfo::getPrefetchDistance() const {
+ return TTIImpl->getPrefetchDistance();
+}
+
unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
return TTIImpl->getMaxInterleaveFactor(VF);
}
diff --git a/llvm/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp b/llvm/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp
index c113ae5f52c..14553ab9d57 100644
--- a/llvm/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp
+++ b/llvm/lib/Target/PowerPC/PPCLoopDataPrefetch.cpp
@@ -44,12 +44,6 @@ static cl::opt<bool>
PrefetchWrites("ppc-loop-prefetch-writes", cl::Hidden, cl::init(false),
cl::desc("Prefetch write addresses"));
-// This seems like a reasonable default for the BG/Q (this pass is enabled, by
-// default, only on the BG/Q).
-static cl::opt<unsigned>
-PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
- cl::desc("The loop prefetch distance"));
-
namespace llvm {
void initializePPCLoopDataPrefetchPass(PassRegistry&);
}
@@ -107,6 +101,8 @@ bool PPCLoopDataPrefetch::runOnFunction(Function &F) {
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
assert(TTI->getCacheLineSize() && "Cache line size is not set for target");
+ assert(TTI->getPrefetchDistance() &&
+ "Prefetch distance is not set for target");
bool MadeChange = false;
@@ -147,7 +143,7 @@ bool PPCLoopDataPrefetch::runOnLoop(Loop *L) {
if (!LoopSize)
LoopSize = 1;
- unsigned ItersAhead = PrefDist/LoopSize;
+ unsigned ItersAhead = TTI->getPrefetchDistance() / LoopSize;
if (!ItersAhead)
ItersAhead = 1;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index b60c07c3672..9212e916f59 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -27,6 +27,12 @@ static cl::opt<unsigned>
CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
cl::desc("The loop prefetch cache line size"));
+// This seems like a reasonable default for the BG/Q (this pass is enabled, by
+// default, only on the BG/Q).
+static cl::opt<unsigned>
+PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
+ cl::desc("The loop prefetch distance"));
+
//===----------------------------------------------------------------------===//
//
// PPC cost model.
@@ -242,6 +248,8 @@ unsigned PPCTTIImpl::getCacheLineSize() {
return CacheLineSize;
}
+unsigned PPCTTIImpl::getPrefetchDistance() { return PrefDist; }
+
unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
unsigned Directive = ST->getDarwinDirective();
// The 440 has no SIMD support, but floating-point instructions
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index d216bdfec97..5ea9a543cdb 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -71,6 +71,7 @@ public:
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getCacheLineSize();
+ unsigned getPrefetchDistance();
unsigned getMaxInterleaveFactor(unsigned VF);
int getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
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