diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 32 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 53 |
2 files changed, 72 insertions, 13 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index e2ed98bd423..9c78f047690 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -555,19 +555,6 @@ let Predicates = [HasSVE] in { defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">; defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">; - def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; - def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; - def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">; - - defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">; - defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">; - defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">; - defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">; - defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">; - defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">; - defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">; - defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">; - defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">; defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">; defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">; @@ -612,6 +599,25 @@ let Predicates = [HasSVE] in { defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq">; defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne">; + def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; + def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; + def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">; + + defm CNTB_XPiI : sve_int_count<0b000, "cntb">; + defm CNTH_XPiI : sve_int_count<0b010, "cnth">; + defm CNTW_XPiI : sve_int_count<0b100, "cntw">; + defm CNTD_XPiI : sve_int_count<0b110, "cntd">; + defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp">; + + defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">; + defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">; + defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">; + defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">; + defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">; + defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">; + defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">; + defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">; + defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">; defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">; defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index cc6b5489689..39612a2001f 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -356,11 +356,64 @@ multiclass sve_int_count_v<bits<5> opc, string asm> { def _D : sve_int_count_v<0b11, opc, asm, ZPR64>; } +class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm, + PPRRegOp pprty> +: I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), + asm, "\t$Rd, $Pg, $Pn", + "", + []>, Sched<[]> { + bits<4> Pg; + bits<4> Pn; + bits<5> Rd; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = sz8_64; + let Inst{21-19} = 0b100; + let Inst{18-16} = opc{3-1}; + let Inst{15-14} = 0b10; + let Inst{13-10} = Pg; + let Inst{9} = opc{0}; + let Inst{8-5} = Pn; + let Inst{4-0} = Rd; +} + +multiclass sve_int_pcount_pred<bits<4> opc, string asm> { + def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; + def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; + def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; + def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; +} //===----------------------------------------------------------------------===// // SVE Element Count Group //===----------------------------------------------------------------------===// +class sve_int_count<bits<3> opc, string asm> +: I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4), + asm, "\t$Rd, $pattern, mul $imm4", + "", + []>, Sched<[]> { + bits<5> Rd; + bits<4> imm4; + bits<5> pattern; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{2-1}; + let Inst{21-20} = 0b10; + let Inst{19-16} = imm4; + let Inst{15-11} = 0b11100; + let Inst{10} = opc{0}; + let Inst{9-5} = pattern; + let Inst{4-0} = Rd; +} + +multiclass sve_int_count<bits<3> opc, string asm> { + def NAME : sve_int_count<opc, asm>; + + def : InstAlias<asm # "\t$Rd, $pattern", + (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>; + def : InstAlias<asm # "\t$Rd", + (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>; +} + class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Zdn, $pattern, mul $imm4", |
