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-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp4
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td4
2 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 55987338902..c27136c4730 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -539,10 +539,10 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
SelectionDAG &DAG) {
MVT::ValueType vt = LHS.getValueType();
- assert(vt == MVT::i32 || vt == MVT::f32);
+ assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
//Note: unordered floating point compares should use a non throwing
//compare.
- bool isUnorderedFloat = vt == MVT::f32 &&
+ bool isUnorderedFloat = (vt == MVT::f32 || vt == MVT::f64) &&
(CC >= ISD::SETUO && CC <= ISD::SETUNE);
assert(!isUnorderedFloat && "Unordered float compares are not supported");
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 3371871a7c4..45728ac6078 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -178,6 +178,10 @@ def fcmpes : InstARM<(ops FPRegs:$a, FPRegs:$b),
"fcmpes $a, $b",
[(armcmp FPRegs:$a, FPRegs:$b)]>;
+def fcmped : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
+ "fcmped $a, $b",
+ [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
+
// Floating Point Conversion
// We use bitconvert for moving the data between the register classes.
// The format conversion is done with ARM specific nodes
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