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-rw-r--r--llvm/lib/Target/X86/X86InstrAVX512.td8
-rw-r--r--llvm/lib/Target/X86/X86InstrFPStack.td2
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td4
-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td47
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td42
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td38
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td39
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td138
-rw-r--r--llvm/lib/Target/X86/X86Schedule.td7
-rw-r--r--llvm/lib/Target/X86/X86ScheduleAtom.td5
-rw-r--r--llvm/lib/Target/X86/X86ScheduleBtVer2.td21
-rw-r--r--llvm/lib/Target/X86/X86ScheduleSLM.td2
-rw-r--r--llvm/lib/Target/X86/X86ScheduleZnver1.td18
13 files changed, 59 insertions, 312 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index fb6b7b59731..f18490fee88 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -5058,10 +5058,10 @@ let isCodeGenOnly = 1 in {
defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, WriteFCmp, 1>;
defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512, WriteFCmp, 1>;
}
-defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI, WriteFAdd, 1>;
-defm VANDN : avx512_fp_binop_p<0x55, "vandn", null_frag, HasDQI, WriteFAdd, 0>;
-defm VOR : avx512_fp_binop_p<0x56, "vor", null_frag, HasDQI, WriteFAdd, 1>;
-defm VXOR : avx512_fp_binop_p<0x57, "vxor", null_frag, HasDQI, WriteFAdd, 1>;
+defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI, WriteFLogic, 1>;
+defm VANDN : avx512_fp_binop_p<0x55, "vandn", null_frag, HasDQI, WriteFLogic, 0>;
+defm VOR : avx512_fp_binop_p<0x56, "vor", null_frag, HasDQI, WriteFLogic, 1>;
+defm VXOR : avx512_fp_binop_p<0x57, "vxor", null_frag, HasDQI, WriteFLogic, 1>;
// Patterns catch floating point selects with bitcasted integer logic ops.
multiclass avx512_fp_logical_lowering<string InstrStr, SDNode OpNode,
diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td
index 19a5b406158..e8701be06e9 100644
--- a/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -309,7 +309,7 @@ def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
let Defs = [FPSW] in {
-let SchedRW = [WriteVecLogic] in {
+let SchedRW = [WriteFSign] in {
defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
}
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 6f7b47ad503..cf8b987bc9f 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -95,14 +95,14 @@ multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
pat_rr, d>,
- Sched<[WriteVecLogic]>;
+ Sched<[WriteFLogic]>;
let hasSideEffects = 0, mayLoad = 1 in
def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
pat_rm, d>,
- Sched<[WriteVecLogicLd, ReadAfterLd]>;
+ Sched<[WriteFLogic.Folded, ReadAfterLd]>;
}
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 5139f978fb5..352d4187535 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -163,6 +163,8 @@ defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root
defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
+defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs.
+defm : BWWriteResPair<WriteFLogic, [BWPort5], 1>; // Floating point and/or/xor logicals.
defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1>; // Floating point vector variable shuffles.
defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
@@ -177,6 +179,7 @@ def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
def : WriteRes<WriteVecMove, [BWPort015]>;
defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
+defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector integer and/or/xor.
defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
@@ -187,10 +190,6 @@ defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable ble
defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
-// Vector bitwise operations.
-// These are often used on both floating point and integer vectors.
-defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
-
// Conversion between integer and float.
defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
@@ -380,10 +379,6 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr",
- "(V?)ANDNPD(Y?)rr",
- "(V?)ANDNPS(Y?)rr",
- "(V?)ANDPD(Y?)rr",
- "(V?)ANDPS(Y?)rr",
"VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
@@ -437,9 +432,7 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
- "(V?)UNPCKLPS(Y?)rr",
- "(V?)XORPD(Y?)rr",
- "(V?)XORPS(Y?)rr")>;
+ "(V?)UNPCKLPS(Y?)rr")>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1;
@@ -552,21 +545,13 @@ def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
- "MMX_PANDNirr",
- "MMX_PANDirr",
- "MMX_PORirr",
- "MMX_PXORirr",
"(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVDQA(Y?)rr",
"(V?)MOVDQU(Y?)rr",
"(V?)MOVPQI2QIrr",
"VMOVZPQILo2PQIrr",
- "(V?)PANDN(Y?)rr",
- "(V?)PAND(Y?)rr",
- "VPBLENDD(Y?)rri",
- "(V?)POR(Y?)rr",
- "(V?)PXOR(Y?)rr")>;
+ "VPBLENDD(Y?)rri")>;
def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let Latency = 1;
@@ -1238,17 +1223,11 @@ def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
- "(V?)ANDNPDrm",
- "(V?)ANDNPSrm",
- "(V?)ANDPDrm",
- "(V?)ANDPSrm",
"(V?)INSERTPSrm",
"(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
- "(V?)ORPDrm",
- "(V?)ORPSrm",
"(V?)PACKSSDWrm",
"(V?)PACKSSWBrm",
"(V?)PACKUSDWrm",
@@ -1292,9 +1271,7 @@ def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
"(V?)UNPCKHPDrm",
"(V?)UNPCKHPSrm",
"(V?)UNPCKLPDrm",
- "(V?)UNPCKLPSrm",
- "(V?)XORPDrm",
- "(V?)XORPSrm")>;
+ "(V?)UNPCKLPSrm")>;
def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
let Latency = 6;
@@ -1387,19 +1364,11 @@ def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
- "MMX_PANDirm",
- "MMX_PORirm",
- "MMX_PXORirm",
- "(V?)BLENDPDrmi",
+def: InstRW<[BWWriteResGroup65], (instregex "(V?)BLENDPDrmi",
"(V?)BLENDPSrmi",
"VINSERTF128rm",
"VINSERTI128rm",
- "(V?)PANDNrm",
- "(V?)PANDrm",
- "VPBLENDDrmi",
- "(V?)PORrm",
- "(V?)PXORrm")>;
+ "VPBLENDDrmi")>;
def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
let Latency = 6;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 6976d551bdb..9a8a7be6fe2 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -160,6 +160,8 @@ defm : HWWriteResPair<WriteCvtF2I, [HWPort1], 3>;
defm : HWWriteResPair<WriteCvtI2F, [HWPort1], 4>;
defm : HWWriteResPair<WriteCvtF2F, [HWPort1], 3>;
defm : HWWriteResPair<WriteFMA, [HWPort01], 5>;
+defm : HWWriteResPair<WriteFSign, [HWPort0], 1>;
+defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1>;
defm : HWWriteResPair<WriteFBlend, [HWPort015], 1>;
@@ -173,7 +175,7 @@ def : WriteRes<WriteVecLoad, [HWPort23]> { let Latency = 5; }
def : WriteRes<WriteVecMove, [HWPort015]>;
defm : HWWriteResPair<WriteVecShift, [HWPort0], 1>;
-defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1>;
+defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteVecALU, [HWPort15], 1>;
defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5>;
defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>;
@@ -494,12 +496,6 @@ def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>;
//-- Arithmetic instructions --//
-// FABS.
-def : InstRW<[HWWriteP0], (instregex "ABS_F")>;
-
-// FCHS.
-def : InstRW<[HWWriteP0], (instregex "CHS_F")>;
-
// FCOMPP FUCOMPP.
// r.
def : InstRW<[HWWrite2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
@@ -737,10 +733,6 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr",
- "(V?)ANDNPD(Y?)rr",
- "(V?)ANDNPS(Y?)rr",
- "(V?)ANDPD(Y?)rr",
- "(V?)ANDPS(Y?)rr",
"VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
@@ -756,8 +748,6 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
- "(V?)ORPD(Y?)rr",
- "(V?)ORPS(Y?)rr",
"(V?)PACKSSDW(Y?)rr",
"(V?)PACKSSWB(Y?)rr",
"(V?)PACKUSDW(Y?)rr",
@@ -798,9 +788,7 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
- "(V?)UNPCKLPS(Y?)rr",
- "(V?)XORPD(Y?)rr",
- "(V?)XORPS(Y?)rr")>;
+ "(V?)UNPCKLPS(Y?)rr")>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1;
@@ -925,11 +913,7 @@ def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr",
"(V?)MOVDQU(Y?)rr",
"(V?)MOVPQI2QIrr",
"VMOVZPQILo2PQIrr",
- "(V?)PANDN(Y?)rr",
- "(V?)PAND(Y?)rr",
- "VPBLENDD(Y?)rri",
- "(V?)POR(Y?)rr",
- "(V?)PXOR(Y?)rr")>;
+ "VPBLENDD(Y?)rri")>;
def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let Latency = 1;
@@ -1041,13 +1025,7 @@ def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLWDrm",
- "(V?)ANDNPDrm",
- "(V?)ANDNPSrm",
- "(V?)ANDPDrm",
- "(V?)ANDPSrm",
"(V?)INSERTPSrm",
- "(V?)ORPDrm",
- "(V?)ORPSrm",
"(V?)PACKSSDWrm",
"(V?)PACKSSWBrm",
"(V?)PACKUSDWrm",
@@ -1075,9 +1053,7 @@ def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLWDrm",
"(V?)UNPCKHPDrm",
"(V?)UNPCKHPSrm",
"(V?)UNPCKLPDrm",
- "(V?)UNPCKLPSrm",
- "(V?)XORPDrm",
- "(V?)XORPSrm")>;
+ "(V?)UNPCKLPSrm")>;
def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 8;
@@ -1310,11 +1286,7 @@ def: InstRW<[HWWriteResGroup17], (instregex "(V?)BLENDPDrmi",
"(V?)BLENDPSrmi",
"VINSERTF128rm",
"VINSERTI128rm",
- "(V?)PANDNrm",
- "(V?)PANDrm",
- "VPBLENDDrmi",
- "(V?)PORrm",
- "(V?)PXORrm")>;
+ "VPBLENDDrmi")>;
def HWWriteResGroup17_1 : SchedWriteRes<[HWPort23,HWPort015]> {
let Latency = 6;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 429d6ad3825..ee094613504 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -149,6 +149,8 @@ defm : SBWriteResPair<WriteFSqrt, [SBPort0], 14>;
defm : SBWriteResPair<WriteCvtF2I, [SBPort1], 3>;
defm : SBWriteResPair<WriteCvtI2F, [SBPort1], 4>;
defm : SBWriteResPair<WriteCvtF2F, [SBPort1], 3>;
+defm : SBWriteResPair<WriteFSign, [SBPort5], 1>;
+defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteFBlend, [SBPort05], 1>;
@@ -160,7 +162,7 @@ def : WriteRes<WriteVecLoad, [SBPort23]> { let Latency = 6; }
def : WriteRes<WriteVecMove, [SBPort05]>;
defm : SBWriteResPair<WriteVecShift, [SBPort5], 1>;
-defm : SBWriteResPair<WriteVecLogic, [SBPort5], 1>;
+defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteVecALU, [SBPort1], 3>;
defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>;
defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; // TODO this is probably wrong for 256/512-bit for the "generic" model
@@ -451,11 +453,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr",
"MOVDQArr", //TODO: Why are these separated from their VEX equivalent
"MOVDQUrr", // TODO: Why are these separated from their VEX equivalent
"(V?)MOVPQI2QIrr",
- "(V?)MOVZPQILo2PQIrr",
- "(V?)PANDNrr",
- "(V?)PANDrr",
- "(V?)PORrr",
- "(V?)PXORrr")>;
+ "(V?)MOVZPQILo2PQIrr")>;
def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
let Latency = 2;
@@ -967,7 +965,11 @@ def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup52], (instregex "LODSL",
- "LODSQ")>;
+ "LODSQ",
+ "MMX_PANDirm",
+ "MMX_PANDNirm",
+ "MMX_PORirm",
+ "MMX_PXORirm")>;
def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 6;
@@ -1012,18 +1014,12 @@ def SBWriteResGroup56 : SchedWriteRes<[SBPort5,SBPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup56], (instregex "(V?)ANDNPDrm",
- "(V?)ANDNPSrm",
- "(V?)ANDPDrm",
- "(V?)ANDPSrm",
- "VBROADCASTF128",
+def: InstRW<[SBWriteResGroup56], (instregex "VBROADCASTF128",
"(V?)INSERTPSrm",
"(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
- "(V?)ORPDrm",
- "(V?)ORPSrm",
"VPERMILPDmi",
"VPERMILPDrm",
"VPERMILPSmi",
@@ -1033,9 +1029,7 @@ def: InstRW<[SBWriteResGroup56], (instregex "(V?)ANDNPDrm",
"(V?)UNPCKHPDrm",
"(V?)UNPCKHPSrm",
"(V?)UNPCKLPDrm",
- "(V?)UNPCKLPSrm",
- "(V?)XORPDrm",
- "(V?)XORPSrm")>;
+ "(V?)UNPCKLPSrm")>;
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
@@ -1130,16 +1124,6 @@ def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm",
"(V?)PUNPCKLQDQrm",
"(V?)PUNPCKLWDrm")>;
-def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> {
- let Latency = 7;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup60], (instregex "(V?)PANDNrm",
- "(V?)PANDrm",
- "(V?)PORrm",
- "(V?)PXORrm")>;
-
def SBWriteResGroup61 : SchedWriteRes<[SBPort0,SBPort05]> {
let Latency = 7;
let NumMicroOps = 3;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index d09e6707edd..72d15a36d8a 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -160,6 +160,8 @@ defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square ro
defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.
defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.
defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.
+defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs.
+defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1>; // Floating point vector shuffles.
defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends.
@@ -174,6 +176,7 @@ def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;
def : WriteRes<WriteVecMove, [SKLPort015]>;
defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals.
+defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1, [1], 1, 6>; // Vector integer and/or/xor.
defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts.
defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.
defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>;
@@ -184,10 +187,6 @@ defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable b
defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.
defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3>; // Vector PSADBW.
-// Vector bitwise operations.
-// These are often used on both floating point and integer vectors.
-defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor.
-
// Conversion between integer and float.
defm : SKLWriteResPair<WriteCvtF2I, [SKLPort1], 3>; // Float -> Integer.
defm : SKLWriteResPair<WriteCvtI2F, [SKLPort1], 4>; // Integer -> Float.
@@ -565,11 +564,7 @@ def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup9], (instregex "(V?)ANDNPD(Y?)rr",
- "(V?)ANDNPS(Y?)rr",
- "(V?)ANDPD(Y?)rr",
- "(V?)ANDPS(Y?)rr",
- "(V?)BLENDPD(Y?)rri",
+def: InstRW<[SKLWriteResGroup9], (instregex "(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVAPD(Y?)rr",
"(V?)MOVAPS(Y?)rr",
@@ -579,23 +574,15 @@ def: InstRW<[SKLWriteResGroup9], (instregex "(V?)ANDNPD(Y?)rr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
"(V?)MOVZPQILo2PQIrr",
- "(V?)ORPD(Y?)rr",
- "(V?)ORPS(Y?)rr",
"(V?)PADDB(Y?)rr",
"(V?)PADDD(Y?)rr",
"(V?)PADDQ(Y?)rr",
"(V?)PADDW(Y?)rr",
- "(V?)PANDN(Y?)rr",
- "(V?)PAND(Y?)rr",
"VPBLENDD(Y?)rri",
- "(V?)POR(Y?)rr",
"(V?)PSUBB(Y?)rr",
"(V?)PSUBD(Y?)rr",
"(V?)PSUBQ(Y?)rr",
- "(V?)PSUBW(Y?)rr",
- "(V?)PXOR(Y?)rr",
- "(V?)XORPD(Y?)rr",
- "(V?)XORPS(Y?)rr")>;
+ "(V?)PSUBW(Y?)rr")>;
def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let Latency = 1;
@@ -1605,35 +1592,23 @@ def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup91], (instregex "(V?)ANDNPDrm",
- "(V?)ANDNPSrm",
- "(V?)ANDPDrm",
- "(V?)ANDPSrm",
- "(V?)BLENDPDrmi",
+def: InstRW<[SKLWriteResGroup91], (instregex "(V?)BLENDPDrmi",
"(V?)BLENDPSrmi",
"(V?)INSERTF128rm",
"(V?)INSERTI128rm",
"(V?)MASKMOVPDrm",
"(V?)MASKMOVPSrm",
- "(V?)ORPDrm",
- "(V?)ORPSrm",
"(V?)PADDBrm",
"(V?)PADDDrm",
"(V?)PADDQrm",
"(V?)PADDWrm",
- "(V?)PANDNrm",
- "(V?)PANDrm",
"(V?)PBLENDDrmi",
"(V?)PMASKMOVDrm",
"(V?)PMASKMOVQrm",
- "(V?)PORrm",
"(V?)PSUBBrm",
"(V?)PSUBDrm",
"(V?)PSUBQrm",
- "(V?)PSUBWrm",
- "(V?)PXORrm",
- "(V?)XORPDrm",
- "(V?)XORPSrm")>;
+ "(V?)PSUBWrm")>;
def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index df349202795..aa2a8b24870 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -160,6 +160,8 @@ defm : SKXWriteResPair<WriteFSqrt, [SKXPort0], 15>; // Floating point square ro
defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 5>; // Floating point reciprocal estimate.
defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 5>; // Floating point reciprocal square root estimate.
defm : SKXWriteResPair<WriteFMA, [SKXPort015], 4>; // Fused Multiply Add.
+defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
+defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1>; // Floating point vector shuffles.
defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1>; // Floating point vector variable shuffles.
defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1>; // Floating point vector blends.
@@ -174,6 +176,7 @@ def : WriteRes<WriteVecStore, [SKXPort237, SKXPort4]>;
def : WriteRes<WriteVecMove, [SKXPort015]>;
defm : SKXWriteResPair<WriteVecALU, [SKXPort15], 1>; // Vector integer ALU op, no logicals.
+defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1, [1], 1, 6>; // Vector integer and/or/xor.
defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1>; // Vector integer shifts.
defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multiply.
defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply.
@@ -184,10 +187,6 @@ defm : SKXWriteResPair<WriteVarBlend, [SKXPort5], 2, [2]>; // Vector variable b
defm : SKXWriteResPair<WriteMPSAD, [SKXPort0, SKXPort5], 6, [1, 2]>; // Vector MPSAD.
defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3>; // Vector PSADBW.
-// Vector bitwise operations.
-// These are often used on both floating point and integer vectors.
-defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1>; // Vector and/or/xor.
-
// Conversion between integer and float.
defm : SKXWriteResPair<WriteCvtF2I, [SKXPort1], 3>; // Float -> Integer.
defm : SKXWriteResPair<WriteCvtI2F, [SKXPort1], 4>; // Integer -> Float.
@@ -1026,11 +1025,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
- "ANDNPSrr",
- "ANDPDrr",
- "ANDPSrr",
- "BLENDPDrri",
+def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPDrri",
"BLENDPSrri",
"MOVAPDrr",
"MOVAPSrr",
@@ -1039,40 +1034,14 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"MOVPQI2QIrr",
"MOVUPDrr",
"MOVUPSrr",
- "ORPDrr",
- "ORPSrr",
"PADDBrr",
"PADDDrr",
"PADDQrr",
"PADDWrr",
- "PANDNrr",
- "PANDrr",
- "PORrr",
"PSUBBrr",
"PSUBDrr",
"PSUBQrr",
"PSUBWrr",
- "PXORrr",
- "VANDNPDYrr",
- "VANDNPDZ128rr",
- "VANDNPDZ256rr",
- "VANDNPDZrr",
- "VANDNPDrr",
- "VANDNPSYrr",
- "VANDNPSZ128rr",
- "VANDNPSZ256rr",
- "VANDNPSZrr",
- "VANDNPSrr",
- "VANDPDYrr",
- "VANDPDZ128rr",
- "VANDPDZ256rr",
- "VANDPDZrr",
- "VANDPDrr",
- "VANDPSYrr",
- "VANDPSZ128rr",
- "VANDPSZ256rr",
- "VANDPSZrr",
- "VANDPSrr",
"VBLENDMPDZ128rr",
"VBLENDMPDZ256rr",
"VBLENDMPDZrr",
@@ -1128,16 +1097,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VMOVUPSYrr",
"VMOVUPSrr",
"VMOVZPQILo2PQIrr",
- "VORPDYrr",
- "VORPDZ128rr",
- "VORPDZ256rr",
- "VORPDZrr",
- "VORPDrr",
- "VORPSYrr",
- "VORPSZ128rr",
- "VORPSZ256rr",
- "VORPSZrr",
- "VORPSrr",
"VPADDBYrr",
"VPADDBZ128rr",
"VPADDBZ256rr",
@@ -1158,22 +1117,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPADDWZ256rr",
"VPADDWZrr",
"VPADDWrr",
- "VPANDDZ128rr",
- "VPANDDZ256rr",
- "VPANDDZrr",
- "VPANDNDZ128rr",
- "VPANDNDZ256rr",
- "VPANDNDZrr",
- "VPANDNQZ128rr",
- "VPANDNQZ256rr",
- "VPANDNQZrr",
- "VPANDNYrr",
- "VPANDNrr",
- "VPANDQZ128rr",
- "VPANDQZ256rr",
- "VPANDQZrr",
- "VPANDYrr",
- "VPANDrr",
"VPBLENDDYrri",
"VPBLENDDrri",
"VPBLENDMBZ128rr",
@@ -1188,14 +1131,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPBLENDMWZ128rr",
"VPBLENDMWZ256rr",
"VPBLENDMWZrr",
- "VPORDZ128rr",
- "VPORDZ256rr",
- "VPORDZrr",
- "VPORQZ128rr",
- "VPORQZ256rr",
- "VPORQZrr",
- "VPORYrr",
- "VPORrr",
"VPSUBBYrr",
"VPSUBBZ128rr",
"VPSUBBZ256rr",
@@ -1220,27 +1155,7 @@ def: InstRW<[SKXWriteResGroup9], (instregex "ANDNPDrr",
"VPTERNLOGDZrri",
"VPTERNLOGQZ128rri",
"VPTERNLOGQZ256rri",
- "VPTERNLOGQZrri",
- "VPXORDZ128rr",
- "VPXORDZ256rr",
- "VPXORDZrr",
- "VPXORQZ128rr",
- "VPXORQZ256rr",
- "VPXORQZrr",
- "VPXORYrr",
- "VPXORrr",
- "VXORPDYrr",
- "VXORPDZ128rr",
- "VXORPDZ256rr",
- "VXORPDZrr",
- "VXORPDrr",
- "VXORPSYrr",
- "VXORPSZ128rr",
- "VXORPSZ256rr",
- "VXORPSZrr",
- "VXORPSrr",
- "XORPDrr",
- "XORPSrr")>;
+ "VPTERNLOGQZrri")>;
def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let Latency = 1;
@@ -3346,34 +3261,16 @@ def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
- "ANDNPSrm",
- "ANDPDrm",
- "ANDPSrm",
- "BLENDPDrmi",
+def: InstRW<[SKXWriteResGroup95], (instregex "BLENDPDrmi",
"BLENDPSrmi",
- "ORPDrm",
- "ORPSrm",
"PADDBrm",
"PADDDrm",
"PADDQrm",
"PADDWrm",
- "PANDNrm",
- "PANDrm",
- "PORrm",
"PSUBBrm",
"PSUBDrm",
"PSUBQrm",
"PSUBWrm",
- "PXORrm",
- "VANDNPDZ128rm(b?)",
- "VANDNPDrm",
- "VANDNPSZ128rm(b?)",
- "VANDNPSrm",
- "VANDPDZ128rm(b?)",
- "VANDPDrm",
- "VANDPSZ128rm(b?)",
- "VANDPSrm",
"VBLENDMPDZ128rm(b?)",
"VBLENDMPSZ128rm(b?)",
"VBLENDPDrmi",
@@ -3398,10 +3295,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VMOVSLDUPZ128rm(b?)",
"VMOVUPDZ128rm(b?)",
"VMOVUPSZ128rm(b?)",
- "VORPDZ128rm(b?)",
- "VORPDrm",
- "VORPSZ128rm(b?)",
- "VORPSrm",
"VPADDBZ128rm(b?)",
"VPADDBrm",
"VPADDDZ128rm(b?)",
@@ -3410,12 +3303,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPADDQrm",
"VPADDWZ128rm(b?)",
"VPADDWrm",
- "VPANDDZ128rm(b?)",
- "VPANDNDZ128rm(b?)",
- "VPANDNQZ128rm(b?)",
- "VPANDNrm",
- "VPANDQZ128rm(b?)",
- "VPANDrm",
"VPBLENDDrmi",
"VPBLENDMBZ128rm(b?)",
"VPBLENDMDZ128rm(b?)",
@@ -3425,8 +3312,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPBROADCASTQZ128m(b?)",
"VPMASKMOVDrm",
"VPMASKMOVQrm",
- "VPORDZ128rm(b?)",
- "VPORQZ128rm(b?)",
"VPORrm",
"VPSUBBZ128rm(b?)",
"VPSUBBrm",
@@ -3437,16 +3322,7 @@ def: InstRW<[SKXWriteResGroup95], (instregex "ANDNPDrm",
"VPSUBWZ128rm(b?)",
"VPSUBWrm",
"VPTERNLOGDZ128rm(b?)i",
- "VPTERNLOGQZ128rm(b?)i",
- "VPXORDZ128rm(b?)",
- "VPXORQZ128rm(b?)",
- "VPXORrm",
- "VXORPDZ128rm(b?)",
- "VXORPDrm",
- "VXORPSZ128rm(b?)",
- "VXORPSrm",
- "XORPDrm",
- "XORPSrm")>;
+ "VPTERNLOGQZ128rm(b?)i")>;
def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 7;
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index dd2ffeddf49..3ded4121947 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -87,6 +87,8 @@ defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate.
defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
+defm WriteFSign : X86SchedWritePair; // Floating point fabs/fchs.
+defm WriteFLogic : X86SchedWritePair; // Floating point and/or/xor logicals.
defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles.
defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
@@ -104,6 +106,7 @@ def WriteVecLoad : SchedWrite;
def WriteVecStore : SchedWrite;
def WriteVecMove : SchedWrite;
defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals.
+defm WriteVecLogic : X86SchedWritePair; // Vector integer and/or/xor logicals.
defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply.
defm WritePMULLD : X86SchedWritePair; // PMULLD
@@ -114,10 +117,6 @@ defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
defm WritePSADBW : X86SchedWritePair; // Vector PSADBW.
defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
-// Vector bitwise operations.
-// These are often used on both floating point and integer vectors.
-defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
-
// MOVMSK operations.
def WriteFMOVMSK : SchedWrite;
def WriteVecMOVMSK : SchedWrite;
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index a76cdce3883..94c88c5258c 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -210,6 +210,8 @@ defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4,
defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;
defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
+defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>;
+defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;
defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;
defm : AtomWriteResPair<WriteFVarShuffle, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteFMA, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
@@ -351,8 +353,7 @@ def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
let ResourceCycles = [1];
}
def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
-def : InstRW<[AtomWrite1_1], (instregex "ABS_F", "CHS_F",
- "UCOM_F(P|PP)?r",
+def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r",
"BT(C|R|S)?(16|32|64)(rr|ri8)")>;
def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 681d8fcbb15..14d60e56768 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -300,6 +300,8 @@ defm : JWriteResFpuPair<WriteFRcp, [JFPU1, JFPM], 2>;
defm : JWriteResFpuPair<WriteFRsqrt, [JFPU1, JFPM], 2>;
defm : JWriteResFpuPair<WriteFDiv, [JFPU1, JFPM], 19, [1, 19]>;
defm : JWriteResFpuPair<WriteFSqrt, [JFPU1, JFPM], 21, [1, 21]>;
+defm : JWriteResFpuPair<WriteFSign, [JFPU1, JFPM], 2>;
+defm : JWriteResFpuPair<WriteFLogic, [JFPU01, JFPX], 1>;
defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>;
defm : JWriteResFpuPair<WriteFVarShuffle, [JFPU01, JFPX], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteFBlend, [JFPU01, JFPX], 1>;
@@ -532,25 +534,6 @@ def : InstRW<[JWriteCVTPH2PSYLd], (instrs VCVTPH2PSYrm)>;
// AVX instructions.
////////////////////////////////////////////////////////////////////////////////
-def JWriteFLogic: SchedWriteRes<[JFPU01, JFPX]> {
-}
-def : InstRW<[JWriteFLogic], (instrs ORPDrr, ORPSrr, VORPDrr, VORPSrr,
- XORPDrr, XORPSrr, VXORPDrr, VXORPSrr,
- ANDPDrr, ANDPSrr, VANDPDrr, VANDPSrr,
- ANDNPDrr, ANDNPSrr, VANDNPDrr, VANDNPSrr)>;
-
-def JWriteFLogicLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
- let Latency = 6;
-}
-def : InstRW<[JWriteFLogicLd, ReadAfterLd], (instrs ORPDrm, ORPSrm,
- VORPDrm, VORPSrm,
- XORPDrm, XORPSrm,
- VXORPDrm, VXORPSrm,
- ANDPDrm, ANDPSrm,
- VANDPDrm, VANDPSrm,
- ANDNPDrm, ANDNPSrm,
- VANDNPDrm, VANDNPSrm)>;
-
def JWriteFLogicY: SchedWriteRes<[JFPU01, JFPX]> {
let ResourceCycles = [2, 2];
let NumMicroOps = 2;
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index badf5e8f8e4..d62286d04cd 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -135,6 +135,8 @@ defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0], 15>;
defm : SLMWriteResPair<WriteCvtF2I, [SLM_FPC_RSV01], 4>;
defm : SLMWriteResPair<WriteCvtI2F, [SLM_FPC_RSV01], 4>;
defm : SLMWriteResPair<WriteCvtF2F, [SLM_FPC_RSV01], 4>;
+defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 051b2e46fc5..1df972f1329 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -202,6 +202,8 @@ defm : ZnWriteResFpuPair<WriteCvtI2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2I, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteFDiv, [ZnFPU3], 15>;
+defm : ZnWriteResFpuPair<WriteFSign, [ZnFPU3], 2>;
+defm : ZnWriteResFpuPair<WriteFLogic, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU0], 5>;
@@ -778,10 +780,6 @@ def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>;
//-- Arithmetic instructions --//
-def ZnWriteFPU3Lat2 : SchedWriteRes<[ZnFPU3]> {
- let Latency = 2;
-}
-
def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ;
def ZnWriteFPU0Lat1 : SchedWriteRes<[ZnFPU0]> ;
@@ -790,9 +788,6 @@ def ZnWriteFPU0Lat1Ld : SchedWriteRes<[ZnAGU, ZnFPU0]> {
let Latency = 8;
}
-// FABS.
-def : InstRW<[ZnWriteFPU3Lat2], (instregex "ABS_F")>;
-
// FCHS.
def : InstRW<[ZnWriteFPU3Lat1], (instregex "CHS_F")>;
@@ -1672,15 +1667,6 @@ def ZnWriteRSQRTPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
}
def : InstRW<[ZnWriteRSQRTPSYLd], (instregex "VRSQRTPSYm")>;
-//-- Logic instructions --//
-
-// AND, ANDN, OR, XOR PS/PD.
-// x,x / v,v,v.
-def : InstRW<[WriteVecLogic], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
-// x,m / v,v,m.
-def : InstRW<[WriteVecLogicLd],
- (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
-
//-- Other instructions --//
// VZEROUPPER.
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