diff options
Diffstat (limited to 'llvm/lib')
37 files changed, 89 insertions, 89 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index 123d50cb39a..c663646f75f 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -233,7 +233,7 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { void emitBuckets() const; void emitStringOffsets() const; void emitAbbrevs() const; - void emitEntry(const DataT &Data) const; + void emitEntry(const DataT &Entry) const; void emitData() const; public: diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h index 395a6e37828..6a0da5f993d 100644 --- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h +++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h @@ -225,7 +225,7 @@ class LLVM_LIBRARY_VISIBILITY CodeViewDebug : public DebugHandlerBase { using FileToFilepathMapTy = std::map<const DIFile *, std::string>; FileToFilepathMapTy FileToFilepathMap; - StringRef getFullFilepath(const DIFile *S); + StringRef getFullFilepath(const DIFile *File); unsigned maybeRecordFile(const DIFile *F); @@ -386,7 +386,7 @@ protected: void endFunctionImpl(const MachineFunction *) override; public: - CodeViewDebug(AsmPrinter *Asm); + CodeViewDebug(AsmPrinter *AP); void setSymbolSize(const MCSymbol *, uint64_t) override {} diff --git a/llvm/lib/CodeGen/AsmPrinter/DIEHash.h b/llvm/lib/CodeGen/AsmPrinter/DIEHash.h index 85f2fea937f..a47b2669ee4 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DIEHash.h +++ b/llvm/lib/CodeGen/AsmPrinter/DIEHash.h @@ -44,7 +44,7 @@ public: // Helper routines to process parts of a DIE. private: /// Adds the parent context of \param Die to the hash. - void addParentContext(const DIE &Die); + void addParentContext(const DIE &Parent); /// Adds the attributes of \param Die to the hash. void addAttributes(const DIE &Die); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h index 5aea16acdc1..51e1558fe4a 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h @@ -217,7 +217,7 @@ public: DbgVariable *getExistingAbstractVariable(InlinedVariable IV, const DILocalVariable *&Cleansed); DbgVariable *getExistingAbstractVariable(InlinedVariable IV); - void createAbstractVariable(const DILocalVariable *DV, LexicalScope *Scope); + void createAbstractVariable(const DILocalVariable *Var, LexicalScope *Scope); /// Set the skeleton unit associated with this unit. void setSkeleton(DwarfCompileUnit &Skel) { Skeleton = &Skel; } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h index 528f83d2e4b..42988d53b8b 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h @@ -331,9 +331,9 @@ class DwarfDebug : public DebugHandlerBase { using InlinedVariable = DbgValueHistoryMap::InlinedVariable; - void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable Var, + void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable IV, const MDNode *Scope); - void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable Var, + void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable IV, const MDNode *Scope); DbgVariable *createConcreteVariable(DwarfCompileUnit &TheCU, diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h index 08c6f455d76..69696f62653 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h @@ -98,7 +98,7 @@ protected: /// corresponds to the MDNode mapped with the subprogram DIE. DenseMap<DIE *, const DINode *> ContainingTypeMap; - DwarfUnit(dwarf::Tag, const DICompileUnit *CU, AsmPrinter *A, DwarfDebug *DW, + DwarfUnit(dwarf::Tag, const DICompileUnit *Node, AsmPrinter *A, DwarfDebug *DW, DwarfFile *DWU); bool applySubprogramDefinitionAttributes(const DISubprogram *SP, DIE &SPDie); @@ -187,7 +187,7 @@ public: /// Add a dwarf op address data and value using the form given and an /// op of either DW_FORM_addr or DW_FORM_GNU_addr_index. - void addOpAddress(DIELoc &Die, const MCSymbol *Label); + void addOpAddress(DIELoc &Die, const MCSymbol *Sym); /// Add a label delta attribute data and value. void addLabelDelta(DIE &Die, dwarf::Attribute Attribute, const MCSymbol *Hi, @@ -203,7 +203,7 @@ public: void addDIETypeSignature(DIE &Die, uint64_t Signature); /// Add block data. - void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Block); + void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Loc); /// Add block data. void addBlock(DIE &Die, dwarf::Attribute Attribute, DIEBlock *Block); @@ -260,7 +260,7 @@ public: bool SkipSPAttributes = false); /// Find existing DIE or create new DIE for the given type. - DIE *getOrCreateTypeDIE(const MDNode *N); + DIE *getOrCreateTypeDIE(const MDNode *TyNode); /// Get context owner's DIE. DIE *getOrCreateContextDIE(const DIScope *Context); @@ -342,7 +342,7 @@ protected: private: void constructTypeDIE(DIE &Buffer, const DIBasicType *BTy); void constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy); - void constructTypeDIE(DIE &Buffer, const DISubroutineType *DTy); + void constructTypeDIE(DIE &Buffer, const DISubroutineType *CTy); void constructSubrangeDIE(DIE &Buffer, const DISubrange *SR, DIE *IndexTy); void constructArrayTypeDIE(DIE &Buffer, const DICompositeType *CTy); void constructEnumTypeDIE(DIE &Buffer, const DICompositeType *CTy); diff --git a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.h b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.h index ab3bd5d419f..b89421a1e06 100644 --- a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.h +++ b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.h @@ -72,7 +72,7 @@ protected: /// Compute the actions table and gather the first action index for each /// landing pad site. - void computeActionsTable(const SmallVectorImpl<const LandingPadInfo *> &LPs, + void computeActionsTable(const SmallVectorImpl<const LandingPadInfo *> &LandingPads, SmallVectorImpl<ActionEntry> &Actions, SmallVectorImpl<unsigned> &FirstActions); @@ -86,7 +86,7 @@ protected: /// no entry and must not be contained in the try-range of any entry - they /// form gaps in the table. Entries must be ordered by try-range address. void computeCallSiteTable(SmallVectorImpl<CallSiteEntry> &CallSites, - const SmallVectorImpl<const LandingPadInfo *> &LPs, + const SmallVectorImpl<const LandingPadInfo *> &LandingPads, const SmallVectorImpl<unsigned> &FirstActions); /// Emit landing pads and actions. diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index 460e7055d9b..f2615edaece 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -98,8 +98,8 @@ namespace { CreateCmpXchgInstFun CreateCmpXchg); bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI); - bool isIdempotentRMW(AtomicRMWInst *AI); - bool simplifyIdempotentRMW(AtomicRMWInst *AI); + bool isIdempotentRMW(AtomicRMWInst *RMWI); + bool simplifyIdempotentRMW(AtomicRMWInst *RMWI); bool expandAtomicOpToLibcall(Instruction *I, unsigned Size, unsigned Align, Value *PointerOperand, Value *ValueOperand, diff --git a/llvm/lib/CodeGen/BranchFolding.h b/llvm/lib/CodeGen/BranchFolding.h index 838f45a5851..accd0ab7317 100644 --- a/llvm/lib/CodeGen/BranchFolding.h +++ b/llvm/lib/CodeGen/BranchFolding.h @@ -38,11 +38,11 @@ class TargetRegisterInfo; explicit BranchFolder(bool defaultEnableTailMerge, bool CommonHoist, - MBFIWrapper &MBFI, - const MachineBranchProbabilityInfo &MBPI, + MBFIWrapper &FreqInfo, + const MachineBranchProbabilityInfo &ProbInfo, // Min tail length to merge. Defaults to commandline // flag. Ignored for optsize. - unsigned MinCommonTailLength = 0); + unsigned MinTailLength = 0); /// Perhaps branch folding, tail merging and other CFG optimizations on the /// given function. Block placement changes the layout and may create new diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp index 3866f51e93c..c092da2b660 100644 --- a/llvm/lib/CodeGen/BranchRelaxation.cpp +++ b/llvm/lib/CodeGen/BranchRelaxation.cpp @@ -96,7 +96,7 @@ class BranchRelaxation : public MachineFunctionPass { MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI, MachineBasicBlock *DestBB); - void adjustBlockOffsets(MachineBasicBlock &MBB); + void adjustBlockOffsets(MachineBasicBlock &Start); bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const; bool fixupConditionalBranch(MachineInstr &MI); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 3c955396938..c41beb09460 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -321,16 +321,16 @@ class TypePromotionTransaction; bool isPreheader); bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT); bool optimizeInst(Instruction *I, bool &ModifiedDT); - bool optimizeMemoryInst(Instruction *I, Value *Addr, - Type *AccessTy, unsigned AS); + bool optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, + Type *AccessTy, unsigned AddrSpace); bool optimizeInlineAsmInst(CallInst *CS); bool optimizeCallInst(CallInst *CI, bool &ModifiedDT); bool optimizeExt(Instruction *&I); bool optimizeExtUses(Instruction *I); - bool optimizeLoadExt(LoadInst *I); + bool optimizeLoadExt(LoadInst *Load); bool optimizeSelectInst(SelectInst *SI); - bool optimizeShuffleVectorInst(ShuffleVectorInst *SI); - bool optimizeSwitchInst(SwitchInst *CI); + bool optimizeShuffleVectorInst(ShuffleVectorInst *SVI); + bool optimizeSwitchInst(SwitchInst *SI); bool optimizeExtractElementInst(Instruction *Inst); bool dupRetToEnableTailCallOpts(BasicBlock *BB); bool placeDbgValues(Function &F); @@ -2612,8 +2612,8 @@ public: private: bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth); - bool matchAddr(Value *V, unsigned Depth); - bool matchOperationAddr(User *Operation, unsigned Opcode, unsigned Depth, + bool matchAddr(Value *Addr, unsigned Depth); + bool matchOperationAddr(User *AddrInst, unsigned Opcode, unsigned Depth, bool *MovedAway = nullptr); bool isProfitableToFoldIntoAddressingMode(Instruction *I, ExtAddrMode &AMBefore, diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp index d73e2c4670b..d7562cbf1e9 100644 --- a/llvm/lib/CodeGen/ExpandMemCmp.cpp +++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp @@ -102,7 +102,7 @@ class MemCmpExpansion { MemCmpExpansion(CallInst *CI, uint64_t Size, const TargetTransformInfo::MemCmpExpansionOptions &Options, unsigned MaxNumLoads, const bool IsUsedForZeroCmp, - unsigned NumLoadsPerBlockForZeroCmp, const DataLayout &DL); + unsigned MaxLoadsPerBlockForZeroCmp, const DataLayout &TheDataLayout); unsigned getNumBlocks(); uint64_t getNumLoads() const { return LoadSequence.size(); } diff --git a/llvm/lib/CodeGen/GCRootLowering.cpp b/llvm/lib/CodeGen/GCRootLowering.cpp index 4361d8b248c..31ddeadbd97 100644 --- a/llvm/lib/CodeGen/GCRootLowering.cpp +++ b/llvm/lib/CodeGen/GCRootLowering.cpp @@ -38,7 +38,7 @@ namespace { /// directed by the GCStrategy. It also performs automatic root initialization /// and custom intrinsic lowering. class LowerIntrinsics : public FunctionPass { - bool PerformDefaultLowering(Function &F, GCStrategy &Coll); + bool PerformDefaultLowering(Function &F, GCStrategy &S); public: static char ID; @@ -61,7 +61,7 @@ class GCMachineCodeAnalysis : public MachineFunctionPass { const TargetInstrInfo *TII; void FindSafePoints(MachineFunction &MF); - void VisitCallPoint(MachineBasicBlock::iterator MI); + void VisitCallPoint(MachineBasicBlock::iterator CI); MCSymbol *InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL) const; diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 83c168bf686..f12d00071b2 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -252,7 +252,7 @@ namespace { BBInfo &TrueBBI, BBInfo &FalseBBI) const; void AnalyzeBlock(MachineBasicBlock &MBB, std::vector<std::unique_ptr<IfcvtToken>> &Tokens); - bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond, + bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Pred, bool isTriangle = false, bool RevBranch = false, bool hasCommonTail = false); void AnalyzeBlocks(MachineFunction &MF, diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index b3f6e1fc7fe..0a447bc613b 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -115,7 +115,7 @@ class ImplicitNullChecks : public MachineFunctionPass { /// \c canHandle should return true for all instructions in \p /// Insts. DependenceResult computeDependence(const MachineInstr *MI, - ArrayRef<MachineInstr *> Insts); + ArrayRef<MachineInstr *> Block); /// Represents one null check that can be made implicit. class NullCheck { diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index 75527fafaaa..3ff03ec4a7e 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -307,7 +307,7 @@ public: /// splitRegister - Replace OldReg ranges with NewRegs ranges where NewRegs is /// live. Returns true if any changes were made. - bool splitRegister(unsigned OldLocNo, ArrayRef<unsigned> NewRegs, + bool splitRegister(unsigned OldReg, ArrayRef<unsigned> NewRegs, LiveIntervals &LIS); /// rewriteLocations - Rewrite virtual register locations according to the diff --git a/llvm/lib/CodeGen/LiveRangeCalc.h b/llvm/lib/CodeGen/LiveRangeCalc.h index b8502ac880e..9f226b154a6 100644 --- a/llvm/lib/CodeGen/LiveRangeCalc.h +++ b/llvm/lib/CodeGen/LiveRangeCalc.h @@ -147,7 +147,7 @@ class LiveRangeCalc { /// /// PhysReg, when set, is used to verify live-in lists on basic blocks. bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, - SlotIndex Kill, unsigned PhysReg, + SlotIndex Use, unsigned PhysReg, ArrayRef<SlotIndex> Undefs); /// updateSSA - Compute the values that will be live in to all requested diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 63e5d4d8e8c..09ff77b1af9 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -203,7 +203,7 @@ public: bool parseRegisterOperand(MachineOperand &Dest, Optional<unsigned> &TiedDefIdx, bool IsDef = false); bool parseImmediateOperand(MachineOperand &Dest); - bool parseIRConstant(StringRef::iterator Loc, StringRef Source, + bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, const Constant *&C); bool parseIRConstant(StringRef::iterator Loc, const Constant *&C); bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty); @@ -222,7 +222,7 @@ public: bool parseJumpTableIndexOperand(MachineOperand &Dest); bool parseExternalSymbolOperand(MachineOperand &Dest); bool parseMDNode(MDNode *&Node); - bool parseDIExpression(MDNode *&Node); + bool parseDIExpression(MDNode *&Expr); bool parseMetadataOperand(MachineOperand &Dest); bool parseCFIOffset(int &Offset); bool parseCFIRegister(unsigned &Reg); diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.h b/llvm/lib/CodeGen/MIRParser/MIParser.h index e08204407d0..b06ceb21b74 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.h +++ b/llvm/lib/CodeGen/MIRParser/MIParser.h @@ -67,7 +67,7 @@ struct PerFunctionMIParsingState { const Name2RegClassMap &Names2RegClasses, const Name2RegBankMap &Names2RegBanks); - VRegInfo &getVRegInfo(unsigned VReg); + VRegInfo &getVRegInfo(unsigned Num); VRegInfo &getVRegInfoNamed(StringRef RegName); }; diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index 5e39e5326c3..21350df624e 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -425,7 +425,7 @@ class MachineBlockPlacement : public MachineFunctionPass { MachineBasicBlock *BB, MachineBasicBlock *LPred, BlockChain &Chain, BlockFilterSet *BlockFilter, MachineFunction::iterator &PrevUnplacedBlockIt, - bool &DuplicatedToPred); + bool &DuplicatedToLPred); bool hasBetterLayoutPredecessor( const MachineBasicBlock *BB, const MachineBasicBlock *Succ, const BlockChain &SuccChain, BranchProbability SuccProb, @@ -474,7 +474,7 @@ class MachineBlockPlacement : public MachineFunctionPass { /// fallthroughs. bool isProfitableToTailDup( const MachineBasicBlock *BB, const MachineBasicBlock *Succ, - BranchProbability AdjustedSumProb, + BranchProbability QProb, const BlockChain &Chain, const BlockFilterSet *BlockFilter); /// Check for a trellis layout. diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index e2d92009f21..7332b716203 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -216,7 +216,7 @@ namespace { DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren, DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap); - void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode); + void HoistOutOfLoop(MachineDomTreeNode *HeaderN); void HoistRegion(MachineDomTreeNode *N, bool IsHeader); diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 5e1760ef808..9bb00aaef86 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -434,7 +434,7 @@ private: unsigned InstStageNum, SMSchedule &Schedule); void updateInstruction(MachineInstr *NewMI, bool LastDef, - unsigned CurStageNum, unsigned InstStageNum, + unsigned CurStageNum, unsigned InstrStageNum, SMSchedule &Schedule, ValueMapTy *VRMap); MachineInstr *findDefInLoop(unsigned Reg); unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal, @@ -710,7 +710,7 @@ public: void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque<SUnit *> &Insts); bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi); - bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Inst, + bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO); void print(raw_ostream &os) const; void dump() const; diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 310316c491b..d644e41abc5 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -251,16 +251,16 @@ namespace { void report_context_liverange(const LiveRange &LR) const; void report_context_lanemask(LaneBitmask LaneMask) const; void report_context_vreg(unsigned VReg) const; - void report_context_vreg_regunit(unsigned VRegOrRegUnit) const; + void report_context_vreg_regunit(unsigned VRegOrUnit) const; void verifyInlineAsm(const MachineInstr *MI); void checkLiveness(const MachineOperand *MO, unsigned MONum); void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum, - SlotIndex UseIdx, const LiveRange &LR, unsigned Reg, + SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit, LaneBitmask LaneMask = LaneBitmask::getNone()); void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum, - SlotIndex DefIdx, const LiveRange &LR, unsigned Reg, + SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, LaneBitmask LaneMask = LaneBitmask::getNone()); void markReachable(const MachineBasicBlock *MBB); diff --git a/llvm/lib/CodeGen/OptimizePHIs.cpp b/llvm/lib/CodeGen/OptimizePHIs.cpp index 8972867ba08..befa8422d39 100644 --- a/llvm/lib/CodeGen/OptimizePHIs.cpp +++ b/llvm/lib/CodeGen/OptimizePHIs.cpp @@ -45,7 +45,7 @@ namespace { initializeOptimizePHIsPass(*PassRegistry::getPassRegistry()); } - bool runOnMachineFunction(MachineFunction &MF) override; + bool runOnMachineFunction(MachineFunction &Fn) override; void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index b7a5a6d4755..7a5c2000006 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -75,7 +75,7 @@ namespace { initializePHIEliminationPass(*PassRegistry::getPassRegistry()); } - bool runOnMachineFunction(MachineFunction &Fn) override; + bool runOnMachineFunction(MachineFunction &MF) override; void getAnalysisUsage(AnalysisUsage &AU) const override; private: @@ -91,7 +91,7 @@ namespace { /// register which is used in a PHI node. We map that to the BB the /// vreg is coming from. This is used later to determine when the vreg /// is killed in the BB. - void analyzePHINodes(const MachineFunction& Fn); + void analyzePHINodes(const MachineFunction& MF); /// Split critical edges where necessary for good coalescer performance. bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp index 3bc5809090f..7e9b4af12ee 100644 --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -44,7 +44,7 @@ public: void getAnalysisUsage(AnalysisUsage &au) const override; - bool runOnMachineFunction(MachineFunction &fn) override; + bool runOnMachineFunction(MachineFunction &MF) override; }; } // end anonymous namespace diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index e2980d175e7..7b57c6cbcdb 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -179,7 +179,7 @@ namespace { } private: - bool runOnMachineFunction(MachineFunction &Fn) override; + bool runOnMachineFunction(MachineFunction &MF) override; void allocateBasicBlock(MachineBasicBlock &MBB); void handleThroughOperands(MachineInstr &MI, SmallVectorImpl<unsigned> &VirtDead); @@ -206,7 +206,7 @@ namespace { return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); } - LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, MCPhysReg PhysReg); + LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg); LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator, unsigned Hint); LiveRegMap::iterator defineVirtReg(MachineInstr &MI, unsigned OpNum, diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index e8e6cf21f1c..f84874a8b85 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -462,7 +462,7 @@ private: bool calcCompactRegion(GlobalSplitCandidate&); void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>); void calcGapWeights(unsigned, SmallVectorImpl<float>&); - unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); + unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg); bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&); bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg, diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 74fe0fd8b47..02164d9afbe 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -162,7 +162,7 @@ namespace { /// was successfully coalesced away. If it is not currently possible to /// coalesce this interval, but it may be possible if other things get /// coalesced, then it returns true by reference in 'Again'. - bool joinCopy(MachineInstr *TheCopy, bool &Again); + bool joinCopy(MachineInstr *CopyMI, bool &Again); /// Attempt to join these two intervals. On failure, this /// returns false. The output "SrcInt" will not have been modified, so we @@ -2126,7 +2126,7 @@ class JoinVals { /// Find the ultimate value that VNI was copied from. std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const; - bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const; + bool valuesIdentical(VNInfo *Value0, VNInfo *Value1, const JoinVals &Other) const; /// Analyze ValNo in this live range, and set all fields of Vals[ValNo]. /// Return a conflict resolution when possible, but leave the hard cases as diff --git a/llvm/lib/CodeGen/ScheduleDAGPrinter.cpp b/llvm/lib/CodeGen/ScheduleDAGPrinter.cpp index 37c4a470bd0..ff2085aae86 100644 --- a/llvm/lib/CodeGen/ScheduleDAGPrinter.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGPrinter.cpp @@ -61,7 +61,7 @@ namespace llvm { } - std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph); + std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *Graph); static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *Graph) { return "shape=Mrecord"; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 17c483266cc..4799afbb74a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -310,9 +310,9 @@ namespace { SDValue visitUMULO(SDNode *N); SDValue visitIMINMAX(SDNode *N); SDValue visitAND(SDNode *N); - SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference); + SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N); SDValue visitOR(SDNode *N); - SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference); + SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N); SDValue visitXOR(SDNode *N); SDValue SimplifyVBinOp(SDNode *N); SDValue visitSHL(SDNode *N); @@ -392,8 +392,8 @@ namespace { SDValue visitFMULForFMADistributiveCombine(SDNode *N); SDValue XformToShuffleWithZero(SDNode *N); - SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS, - SDValue RHS); + SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0, + SDValue N1); SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt); @@ -431,14 +431,14 @@ namespace { SDValue BuildSDIV(SDNode *N); SDValue BuildSDIVPow2(SDNode *N); SDValue BuildUDIV(SDNode *N); - SDValue BuildLogBase2(SDValue Op, const SDLoc &DL); + SDValue BuildLogBase2(SDValue V, const SDLoc &DL); SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags); SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags); SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags); SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip); - SDValue buildSqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations, + SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations, SDNodeFlags Flags, bool Reciprocal); - SDValue buildSqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations, + SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations, SDNodeFlags Flags, bool Reciprocal); SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, bool DemandHighBits = true); @@ -460,7 +460,7 @@ namespace { SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N, ArrayRef<int> VectorMask, SDValue VecIn1, SDValue VecIn2, unsigned LeftIdx); - SDValue matchVSelectOpSizesWithSetCC(SDNode *N); + SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast); /// Walk up chain skipping non-aliasing memory nodes, /// looking for aliasing nodes and adding them to the Aliases vector. @@ -519,8 +519,8 @@ namespace { /// Used by BackwardsPropagateMask to find suitable loads. bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl<LoadSDNode*> &Loads, - SmallPtrSetImpl<SDNode*> &NodeWithConsts, - ConstantSDNode *Mask, SDNode *&UncombinedNode); + SmallPtrSetImpl<SDNode*> &NodesWithConsts, + ConstantSDNode *Mask, SDNode *&NodeToMask); /// Attempt to propagate a given AND node back to load leaves so that they /// can be combined into narrow loads. bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG); @@ -561,7 +561,7 @@ namespace { /// This optimization uses wide integers or vectors when possible. /// \return number of stores that were merged into a merged store (the /// affected nodes are stored as a prefix in \p StoreNodes). - bool MergeConsecutiveStores(StoreSDNode *N); + bool MergeConsecutiveStores(StoreSDNode *St); /// Try to transform a truncation where C is a constant: /// (trunc (and X, C)) -> (and (trunc X), (trunc C)) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index c272b0d241f..2b7ba1ffb30 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -167,7 +167,7 @@ private: SDValue NewIntValue) const; SDValue ExpandFCOPYSIGN(SDNode *Node) const; SDValue ExpandFABS(SDNode *Node) const; - SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, + SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT, const SDLoc &dl); SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, const SDLoc &dl); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index e4d4aac3340..80b2123c0ff 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -209,7 +209,7 @@ private: SDNode *AnalyzeNewNode(SDNode *N); void AnalyzeNewValue(SDValue &Val); void PerformExpensiveChecks(); - void RemapId(TableId &N); + void RemapId(TableId &Id); void RemapValue(SDValue &V); // Common routines. @@ -332,7 +332,7 @@ private: SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo); // Integer Operand Promotion. - bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo); + bool PromoteIntegerOperand(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N); SDValue PromoteIntOp_BITCAST(SDNode *N); @@ -423,7 +423,7 @@ private: bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi); // Integer Operand Expansion. - bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo); + bool ExpandIntegerOperand(SDNode *N, unsigned OpNo); SDValue ExpandIntOp_BR_CC(SDNode *N); SDValue ExpandIntOp_SELECT_CC(SDNode *N); SDValue ExpandIntOp_SETCC(SDNode *N); @@ -579,7 +579,7 @@ private: void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi); // Float Operand Expansion. - bool ExpandFloatOperand(SDNode *N, unsigned OperandNo); + bool ExpandFloatOperand(SDNode *N, unsigned OpNo); SDValue ExpandFloatOp_BR_CC(SDNode *N); SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N); SDValue ExpandFloatOp_FP_ROUND(SDNode *N); @@ -620,7 +620,7 @@ private: SDValue PromoteFloatRes_UNDEF(SDNode *N); SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N); - bool PromoteFloatOperand(SDNode *N, unsigned ResNo); + bool PromoteFloatOperand(SDNode *N, unsigned OpNo); SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo); SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo); SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo); @@ -645,7 +645,7 @@ private: void SetScalarizedVector(SDValue Op, SDValue Result); // Vector Result Scalarization: <1 x ty> -> ty. - void ScalarizeVectorResult(SDNode *N, unsigned OpNo); + void ScalarizeVectorResult(SDNode *N, unsigned ResNo); SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo); SDValue ScalarizeVecRes_BinOp(SDNode *N); SDValue ScalarizeVecRes_TernaryOp(SDNode *N); @@ -694,7 +694,7 @@ private: void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi); // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>. - void SplitVectorResult(SDNode *N, unsigned OpNo); + void SplitVectorResult(SDNode *N, unsigned ResNo); void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi); @@ -710,9 +710,9 @@ private: void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi); + void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi); + void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi); + void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi); void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi); void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, @@ -732,7 +732,7 @@ private: SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo); SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo); - SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo); + SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo); SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N); SDValue SplitVecOp_VSETCC(SDNode *N); SDValue SplitVecOp_FP_ROUND(SDNode *N); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h index 483acd178f9..6417e16bd0f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h @@ -88,7 +88,7 @@ class InstrItineraryData; /// Clone - Creates a clone of the specified SUnit. It does not copy the /// predecessors / successors info nor the temporary scheduling states. /// - SUnit *Clone(SUnit *N); + SUnit *Clone(SUnit *Old); /// BuildSchedGraph - Build the SUnit graph from the selection dag that we /// are input. This SUnit graph is similar to the SelectionDAG, but diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index c5c02bff793..e421984b8af 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -712,13 +712,13 @@ public: void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, - Instruction::BinaryOps Opc, BranchProbability TW, - BranchProbability FW, bool InvertCond); + Instruction::BinaryOps Opc, BranchProbability TProb, + BranchProbability FProb, bool InvertCond); void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, - BranchProbability TW, BranchProbability FW, + BranchProbability TProb, BranchProbability FProb, bool InvertCond); bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases); bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); @@ -790,11 +790,11 @@ public: }; /// Lower \p SLI into a STATEPOINT instruction. - SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI); + SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI); // This function is responsible for the whole statepoint lowering process. // It uniformly handles invoke and call statepoints. - void LowerStatepoint(ImmutableStatepoint Statepoint, + void LowerStatepoint(ImmutableStatepoint ISP, const BasicBlock *EHPadBB = nullptr); void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee, @@ -897,7 +897,7 @@ private: void visitExtractValue(const User &I); void visitInsertValue(const User &I); - void visitLandingPad(const LandingPadInst &I); + void visitLandingPad(const LandingPadInst &LP); void visitGetElementPtr(const User &I); void visitSelect(const User &I); @@ -942,7 +942,7 @@ private: const BasicBlock *EHPadBB = nullptr); // These two are implemented in StatepointLowering.cpp - void visitGCRelocate(const GCRelocateInst &I); + void visitGCRelocate(const GCRelocateInst &Relocate); void visitGCResult(const GCResultInst &I); void visitVectorReduce(const CallInst &I, unsigned Intrinsic); @@ -1052,7 +1052,7 @@ struct RegsForValue { /// Add this value to the specified inlineasm node operand list. This adds the /// code marker, matching input operand index (if applicable), and includes /// the number of values added into it. - void AddInlineAsmOperands(unsigned Kind, bool HasMatching, + void AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector<SDValue> &Ops) const; diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/lib/CodeGen/SplitKit.h index 2dafaf58780..ed664e4f81a 100644 --- a/llvm/lib/CodeGen/SplitKit.h +++ b/llvm/lib/CodeGen/SplitKit.h @@ -421,7 +421,7 @@ private: SlotIndex buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg, MachineBasicBlock &MB, MachineBasicBlock::iterator InsertBefore, - unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex PrevCopy); + unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def); public: /// Create a new SplitEditor for editing the LiveInterval analyzed by SA. diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp index f9d1eaf0307..81a41970f9e 100644 --- a/llvm/lib/CodeGen/StackColoring.cpp +++ b/llvm/lib/CodeGen/StackColoring.cpp @@ -445,7 +445,7 @@ public: } void getAnalysisUsage(AnalysisUsage &AU) const override; - bool runOnMachineFunction(MachineFunction &MF) override; + bool runOnMachineFunction(MachineFunction &Func) override; private: /// Used in collectMarkers |
