diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 3d73e38efb6..b807fa58b55 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -158,8 +158,9 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW, } } -// A folded store needs a cycle on the SAGU for the store data. -def : WriteRes<WriteRMW, [JSAGU]>; +// A folded store needs a cycle on the SAGU for the store data, +// most RMW instructions don't need an extra uop. +defm : X86WriteRes<WriteRMW, [JSAGU], 1, [1], 0>; //////////////////////////////////////////////////////////////////////////////// // Arithmetic. @@ -208,8 +209,8 @@ defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>; defm : X86WriteRes<WriteBitTestImmLd, [JALU01,JLAGU], 4, [1,1], 1>; defm : X86WriteRes<WriteBitTestRegLd, [JALU01,JLAGU], 4, [1,1], 5>; defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 2>; -defm : X86WriteRes<WriteBitTestSetImmLd, [JALU01,JLAGU], 4, [1,1], 3>; -defm : X86WriteRes<WriteBitTestSetRegLd, [JALU01,JLAGU], 4, [1,1], 7>; +defm : X86WriteRes<WriteBitTestSetImmLd, [JALU01,JLAGU], 4, [1,1], 4>; +defm : X86WriteRes<WriteBitTestSetRegLd, [JALU01,JLAGU], 4, [1,1], 8>; // This is for simple LEAs with one or two input operands. def : WriteRes<WriteLEA, [JALU01]>; |
