diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 30 |
2 files changed, 49 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index f60ff3a4099..50a84a0e525 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -574,6 +574,25 @@ let Predicates = [HasSVE] in { defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">; defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">; + defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>; + defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>; + defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>; + defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>; + defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>; + defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>; + defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>; + defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>; + defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>; + defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>; + defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>; + defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>; + defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>; + defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>; + defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>; + defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>; + defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>; + defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>; + defm INDEX_RR : sve_int_index_rr<"index">; defm INDEX_IR : sve_int_index_ir<"index">; defm INDEX_RI : sve_int_index_ri<"index">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 9acbfb29346..357ac8c8bc1 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -285,6 +285,36 @@ let Predicates = [HasSVE] in { // SVE Element Count Group //===----------------------------------------------------------------------===// +class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), + asm, "\t$Zdn, $pattern, mul $imm4", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> pattern; + bits<4> imm4; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{4-3}; + let Inst{21} = 0b1; + let Inst{20} = opc{2}; + let Inst{19-16} = imm4; + let Inst{15-12} = 0b1100; + let Inst{11-10} = opc{1-0}; + let Inst{9-5} = pattern; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> { + def NAME : sve_int_countvlv<opc, asm, zprty>; + + def : InstAlias<asm # "\t$Zdn, $pattern", + (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>; + def : InstAlias<asm # "\t$Zdn", + (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>; +} + class sve_int_pred_pattern_a<bits<3> opc, string asm> : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Rdn, $pattern, mul $imm4", |
