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-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFormats.td62
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td29
2 files changed, 91 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index ef7d2012a23..152096789c3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -725,6 +725,68 @@ class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = RC;
}
+class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
+ dag OOL, dag IOL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let Pattern = pattern;
+
+ let Inst{6-10} = RST;
+ let Inst{11-12} = xo1;
+ let Inst{13-15} = xo2;
+ let Inst{16-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+ bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let Pattern = pattern;
+ bits<5> FRB;
+
+ let Inst{6-10} = RST;
+ let Inst{11-12} = xo1;
+ let Inst{13-15} = xo2;
+ let Inst{16-20} = FRB;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+ bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let Pattern = pattern;
+ bits<3> DRM;
+
+ let Inst{6-10} = RST;
+ let Inst{11-12} = xo1;
+ let Inst{13-15} = xo2;
+ let Inst{16-17} = 0;
+ let Inst{18-20} = DRM;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
+ bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let Pattern = pattern;
+ bits<2> RM;
+
+ let Inst{6-10} = RST;
+ let Inst{11-12} = xo1;
+ let Inst{13-15} = xo2;
+ let Inst{16-18} = 0;
+ let Inst{19-20} = RM;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+
class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index dd7fc265910..5a79349f6f2 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2571,6 +2571,35 @@ let Uses = [RM] in {
let Defs = [CR1] in
def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
"mffs. $rT", IIC_IntMFFS, []>, isDOT;
+
+ def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
+ "mffsce $rT", IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+ def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
+ (ins f8rc:$FRB), "mffscdrn $rT, $FRB",
+ IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+ def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT),
+ (ins u3imm:$DRM),
+ "mffscdrni $rT, $DRM",
+ IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+ def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT),
+ (ins f8rc:$FRB), "mffscrn $rT, $FRB",
+ IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+ def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
+ (ins u2imm:$RM), "mffscrni $rT, $RM",
+ IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
+
+ def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
+ "mffsl $rT", IIC_IntMFFS, []>,
+ PPC970_DGroup_Single, PPC970_Unit_FPU;
}
let Predicates = [IsISA3_0] in {
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