6 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Analysis/LazyCallGraph.cpp b/llvm/lib/Analysis/LazyCallGraph.cpp
index 50b532c07d0..e0736162a77 100644
--- a/llvm/lib/Analysis/LazyCallGraph.cpp
+++ b/llvm/lib/Analysis/LazyCallGraph.cpp
@@ -423,7 +423,7 @@ void LazyCallGraph::SCC::internalDFS(
         continue;
       }
 
-      // Track the lowest link of the childen, if any are still in the stack.
+      // Track the lowest link of the children, if any are still in the stack.
       // Any child not on the stack will have a LowLink of -1.
       assert(ChildN.LowLink != 0 &&
              "Low-link must not be zero with a non-zero DFS number.");
@@ -654,7 +654,7 @@ LazyCallGraph::SCC *LazyCallGraph::getNextSCCInPostOrder() {
         continue;
       }
 
-      // Track the lowest link of the childen, if any are still in the stack.
+      // Track the lowest link of the children, if any are still in the stack.
       assert(ChildN.LowLink != 0 &&
              "Low-link must not be zero with a non-zero DFS number.");
       if (ChildN.LowLink >= 0 && ChildN.LowLink < N->LowLink)
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 42b9d243f16..92a9a30f24c 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -702,10 +702,10 @@ void ScheduleDAGInstrs::initSUnits() {
 
     // If this SUnit uses a reserved or unbuffered resource, mark it as such.
     //
-    // Reserved resources block an instruction from issueing and stall the
+    // Reserved resources block an instruction from issuing and stall the
     // entire pipeline. These are identified by BufferSize=0.
     //
-    // Unbuffered resources prevent execution of subsequeny instructions that
+    // Unbuffered resources prevent execution of subsequent instructions that
     // require the same resources. This is used for in-order execution pipelines
     // within an out-of-order core. These are identified by BufferSize=1.
     if (SchedModel.hasInstrSchedModel()) {
diff --git a/llvm/lib/MC/WinCOFFObjectWriter.cpp b/llvm/lib/MC/WinCOFFObjectWriter.cpp
index 58f5eccf4d2..2cc027bfa13 100644
--- a/llvm/lib/MC/WinCOFFObjectWriter.cpp
+++ b/llvm/lib/MC/WinCOFFObjectWriter.cpp
@@ -789,7 +789,7 @@ void WinCOFFObjectWriter::RecordRelocation(const MCAssembler &Asm,
     case COFF::IMAGE_REL_ARM_MOV32A:
       // IMAGE_REL_ARM_BRANCH24, IMAGE_REL_ARM_BLX24, IMAGE_REL_ARM_MOV32A are
       // only used for ARM mode code, which is documented as being unsupported
-      // by Windows on ARM.  Emperical proof indicates that masm is able to
+      // by Windows on ARM.  Empirical proof indicates that masm is able to
       // generate the relocations however the rest of the MSVC toolchain is
       // unable to handle it.
       llvm_unreachable("unsupported relocation");
diff --git a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index 304bc561a97..678d0a63ce7 100644
--- a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -163,7 +163,7 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
       return;
     }
 
-    // Otherwise SBFX/UBFX is the prefered form
+    // Otherwise SBFX/UBFX is the preferred form
     O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
       << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
       << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
@@ -190,7 +190,7 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
 
     int LSB = ImmR;
     int Width = ImmS - ImmR + 1;
-    // Otherwise BFXIL the prefered form
+    // Otherwise BFXIL the preferred form
     O << "\tbfxil\t"
       << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
       << ", #" << LSB << ", #" << Width;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6e327aa1326..4e9eecc15ed 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7410,7 +7410,7 @@ static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
   // v4f32 or when copying a member from one v4f32 to another.
   // We also use it for transferring i32 from one register to another,
   // since it simply copies the same bits.
-  // If we're transfering an i32 from memory to a specific element in a
+  // If we're transferring an i32 from memory to a specific element in a
   // register, we output a generic DAG that will match the PINSRD
   // instruction.
   // TODO: Optimize for AVX cases too (VINSERTPS)
diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
index 272fe97b804..0ccf29c225b 100644
--- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -107,7 +107,7 @@ namespace {
 /// In real programs, a GEP index may be more complicated than a simple addition
 /// of something and a constant integer which can be trivially splitted. For
 /// example, to split ((a << 3) | 5) + b, we need to search deeper for the
-/// constant offset, so that we can seperate the index to (a << 3) + b and 5.
+/// constant offset, so that we can separate the index to (a << 3) + b and 5.
 ///
 /// Therefore, this class looks into the expression that computes a given GEP
 /// index, and tries to find a constant integer that can be hoisted to the
@@ -179,7 +179,7 @@ class ConstantOffsetExtractor {
 };
 
 /// \brief A pass that tries to split every GEP in the function into a variadic
-/// base and a constant offset. It is a FuntionPass because searching for the
+/// base and a constant offset. It is a FunctionPass because searching for the
 /// constant offset may inspect other basic blocks.
 class SeparateConstOffsetFromGEP : public FunctionPass {
  public: